decoder and register in Verilog

Discussion in 'Programmer's Corner' started by notwist, Nov 10, 2007.

  1. notwist

    Thread Starter New Member

    Apr 8, 2007
    2
    0
    I'm trying to program the write action for a register file.
    Basically I have 16 instances of a register file whose inputs are:

    enbl - the enable signal
    write_data - data to be written to register
    clk - clock

    and a single output, out, which is the value of the register.

    The problem I'm having is developing a decoder that will set the enbl signal of only a single register to 1 for writing to the register so only 1 register will be written at any given time. All 16 registers will be of the same register module. I am thinking of creating a decoder module that receives the number of the register to be written, and then outputs a 16-bit binary number (called enbl_sig) that will be all 0's except for a single 1 in which the digit place corresponds to the register number to be written. Therefore I can just send enbl[0], enbl[1]... etc to each register instance. The register instance with enbl[.]=1 will be the one that will write the data to the register. Also, the received register number to write to will be received in hexadecimal.

    Sorry if this sounds confusing, but I don't know how else I would be able to do it. Does anyone have any suggestions or perhaps an easier method to accomplish this? I'm trying to program the write action for a register file.
    Basically I have 16 instances of a register file whose inputs are:

    enbl - the enable signal
    write_data - data to be written to register
    clk - clock

    and a single output, out, which is the value of the register.

    The problem I'm having is developing a decoder that will set the enbl signal of only a single register to 1 for writing to the register so only 1 register will be written at any given time. All 16 registers will be of the same register module. I am thinking of creating a decoder module that receives the number of the register to be written, and then outputs a 16-bit binary number (called enbl_sig) that will be all 0's except for a single 1 in which the digit place corresponds to the register number to be written. Therefore I can just send enbl[0], enbl[1]... etc to each register instance. The register instance with enbl[.]=1 will be the one that will write the data to the register. Also, the received register number to write to will be received is a 4-bit hexadecimal number.

    Sorry if this sounds confusing, but I don't know how else I would be able to do it. Does anyone have any suggestions or perhaps an easier method to accomplish this? I don't need the exact code, just the method of taking a 4-bit hexadecimal number and then outputting the desired 16-bit binary number. Thanks again.
    Thanks!
     
  2. jboura

    New Member

    Aug 11, 2007
    1
    0
    there is a lot you can find on the internet in terms of verilog code that addresses this issues. Here is my take.

    module decoder(select,registered_decode_out, clock) ;
    //
    // Always use clocked output into clock enable of registers
    // to avoid any glitching effects resulting from the
    // combinatorial nature of the decoder.
    //
    // have fun - jihad

    input clock ;
    input [3:0] select ;
    output [15:0] registered_decode_out ;

    reg [15:0] registered_decode_out ;
    wire [15:0] decode_out ;

    case (select)
    4'd0 : decode_out <= 16'h0001;
    4'd1 : decode_out <= 16'h0002;
    4'd2 : decode_out <= 16'h0004;
    4'd3 : decode_out <= 16'h0008;
    4'd4 : decode_out <= 16'h0010;
    4'd5 : decode_out <= 16'h0020;
    4'd6 : decode_out <= 16'h0040;
    4'd7 : decode_out <= 16'h0080;
    4'd8 : decode_out <= 16'h0100;
    4'd9 : decode_out <= 16'h0200;
    4'd10 : decode_out <= 16'h0400;
    4'd11 : decode_out <= 16'h0800;
    4'd12 : decode_out <= 16'h1000;
    4'd13 : decode_out <= 16'h2000;
    4'd14 : decode_out <= 16'h4000;
    4'd15 : decode_out <= 16'h8000;
    endcase

    always @ posedge (clock)
    registered_decode_out <= decode_out ;

    endmodule
     
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