Dead time calcultion

Discussion in 'General Electronics Chat' started by SVS, Apr 3, 2014.

  1. SVS

    Thread Starter Member

    Aug 16, 2012
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    Hi everyone,

    Could someone Please help me in calculating the dead time of the waveform attached below??
    i am kinda confused.

    Is there a generalized formula?

    Thank you !
     
  2. MrChips

    Moderator

    Oct 2, 2009
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    What is your definition of dead time?
     
  3. SVS

    Thread Starter Member

    Aug 16, 2012
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    4
    The period during transition time where both the PWM signals are switched OFF.

    Correct me if I am wrong !
     
  4. MrChips

    Moderator

    Oct 2, 2009
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    Then, according to what I see in your scope traces, there is no dead time.
    Worse, both signals are high for about 75ns.
     
  5. SVS

    Thread Starter Member

    Aug 16, 2012
    89
    4
    Ok.. there is no dead dead time between these two signals.
    You are absolutely right.

    But below i have attached the signal ( attachment) which is used to turn on and off my high side and low side MOSFETS .

    According to the data sheet of the MOSFET , it needs min 8 V to turn ON.

    So, looking at the waveform below ,
    At 8V there is still a dead time of 180 ns .
    Am I right ?

    My design needs 150 ns deadtime according to the formula,
    Tdead=16* Ct*fsw*Lm

    Is this sufficient or should I still increase my dead time.

    Please help me out.
     
  6. MrChips

    Moderator

    Oct 2, 2009
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    Yes, I would increase the dead time.
    How are you able to control the dead time?
    Some microcontrollers have PWM outputs with programmable dead time.
     
  7. SVS

    Thread Starter Member

    Aug 16, 2012
    89
    4
    This is exactly my problem , I don' t have programmable dead time micro controller.

    I have to implement it in the hardware. May be increasing the gate resistance of the MOSFET.
    Do You have a better solution??


    Thank you ..
     
  8. MrChips

    Moderator

    Oct 2, 2009
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    Increasing the gate resistance of the MOSFET does not solve the problem because it slows down the decay time at the falling edge.

    There are only two solutions I can think of.

    1) Use a hardware solution using a clock and sychronous timers and decoders,
    2) Use a microcontroller that provides PWM dead time.
     
  9. AnalogKid

    Distinguished Member

    Aug 1, 2013
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    fPlease post as much of the schematic related to the gate drive signals as you can. There may be an analog <gasp> solution. For example, is there one master timing signal that drives one gate directly and the other gate through an inverter, or are the two gate drives coming from the Q and Q- outputs of a flip-flop, or what?

    sch sch sch sch sch sch

    (Schematic 4 and schematic 2, because a good schematic is the answer to life, the universe, and everything.)

    ak
     
  10. MrChips

    Moderator

    Oct 2, 2009
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    I think there is a simple solution using a clocked D-type flip-flop.
    Put the PWM signal into both D-input and CLR' of a 7474 style D-type flip-flop.
    When the signal goes HIGH the Q output will change to HIGH on the next clock pulse.
    When the signal goes LOW, Q will be reset immediately.

    Sorry, AAC wouldn't let be post any more pictures to my album.
     
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  11. crutschow

    Expert

    Mar 14, 2008
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    Here is a circuit to generate non-overlapping clocks. The amount of non-overlap is determined by the number of inverters in the circuit, and the amount of NAND gate and inverter delay. Note that the number of inverters at the output of each NAND gate to the input of the opposite must be an even number (2, 4, 6, etc.).
     
    Last edited: Apr 3, 2014
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  12. AnalogKid

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    Nice, but it's gonna take a loooot of inverters to hit 150 ns. OTOH, with a single RDC delay (or silicon delay line) in each inverter string you eliminate 4 inverters and get any delay you want.

    ak
     
  13. ronv

    AAC Fanatic!

    Nov 12, 2008
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    A whole lot depends on your circuit requirements, but you can improve the situation by adding a gate resistor to slow down the turn on time, then adding a diode in the opposite direction so the turn off time is still fast. The downside of course is that the FET doesn't switch as fast so the power goes up in it.
     
  14. MrChips

    Moderator

    Oct 2, 2009
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    ronv has the right idea.

    Here is a circuit:

    [​IMG]
     
  15. crutschow

    Expert

    Mar 14, 2008
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    Not if you use 4000 series CMOS. ;)
     
  16. SVS

    Thread Starter Member

    Aug 16, 2012
    89
    4
    I already have a gate resistor and a reverse biased Ultrafast diode in paraallel.
    I just have to pick a higher resistance value to increase my dead time.

    I currently have a 10 Ohm resistance , and I will post the results of my waveform with a higher value of resistance .
     
  17. SVS

    Thread Starter Member

    Aug 16, 2012
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    Which IC will get this job done?
     
  18. AnalogKid

    Distinguished Member

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    Based on your drawing, you are using the gate capacitance as part of the delay generator. Probably not a stable idea, because the gate capacitance is not well controlled from one part to the next, and it varies significantly with the temperature of the transistor. Also, to reduce switching losses in the transistors you want rapid turn-ons as well as rapid turnoffs, and you won't get that with the relatively high value gate resistors. A better way is to move your timing circuits to the HIN and LIN pins.

    ak
     
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