Have you considered using the 120 Hz for PWM frequency, somewhat like original SCR but using logic control of FET gate for 0 to 8 msec. delayed turn on ??
Two 555's could be the pattern for logic control. Un filtered rectified V minimum would trigger first 555, adjustable 0 to 8 msec., output C coupled to second 555, output drives gate. Leading edge of # 1 555 is reset to pin 6 of 2 nd 555.
Two 555's could be the pattern for logic control. Un filtered rectified V minimum would trigger first 555, adjustable 0 to 8 msec., output C coupled to second 555, output drives gate. Leading edge of # 1 555 is reset to pin 6 of 2 nd 555.
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