D Type Flip-Flop Circuit

Discussion in 'The Projects Forum' started by MrL, Nov 21, 2009.

  1. MrL

    Thread Starter Member

    Oct 21, 2009
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  2. Ron H

    AAC Fanatic!

    Apr 14, 2005
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    Simulators generally don't assign initial conditions to flip-flop outputs. It looks to me as if, in your first sim the FF output started out low, and in the second sim it started out high. Provide an initial reset pulse before the clock transition. And tie PRN to vcc in all cases.
     
  3. MrL

    Thread Starter Member

    Oct 21, 2009
    46
    0
    Ok, thanks for your help.
     
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