D-latch & D-flip flop

Discussion in 'General Electronics Chat' started by nanobyte, Oct 28, 2005.

  1. nanobyte

    nanobyte Thread Starter Senior Member

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    What is the difference between a D-latch and a D-flip flop? Both seem to be doing the same thing; Q follows D.
  2. Dave

    Dave Retired Moderator

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    Flip-flops are edge triggered, i.e. the output Q will only follow D at the edge of the clock; whether it be rising or falling edge is dependant on the flip flop design.

    Latches are transparent in the enable configuration, i.e. if the latch is enabled the output Q will follow the input D for all changes in D - there is no requirement for an clock edge like for a flip-flop.
  3. isha

    isha Active Member

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    i think both are same
    bcuz they do the same job
  4. Dave

    Dave Retired Moderator

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    Read my post above, they certainly don't do the same things. Flip-flops require clock edges, where as latches only require enabling or disabling. If you consider the output of flip-flops and latches for the same inputs and clock cycle (where for a latch the clock goes to the enable input), you will find that the outputs will be different.

    Look at the attached diagram showing the output of the latch QL and output if the flip-flop QFF for the same inputs and clock cycle. (Note: In this example the latch is enable-high and the flip-flop is rising edge triggered).

    [attachmentid=933]
  5. JoeJester

    JoeJester AAC Fanatic!

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  6. nanobyte

    nanobyte Thread Starter Senior Member

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    What's up everybody. Umm Dave, how come in your diagram the Q output for the flip flop is flat. Shouldn't it have some pulses in response to the clock edges (rising or trailing - which ever one it is suppose to respond to)?
  7. Dave

    Dave Retired Moderator

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    Remember for the flip-flop the input D is latched to the output Q only on the rising edge of the clock. If you look at the diagram, for all rising edges of the clock the input D is low therefore the output Q never changes. (Note, for clarity I have ignored any delays in the timing diagram).

    I have noticed a small error is the output for the latch QL. After the last risng edge of the clock (rising edge number 3) the output QL should go temporarily low, until the input D goes high. Apologies for the mistake.

    Attached is a correction:
  8. blahgod

    blahgod New Member

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    for d FF: d=q on time of clk, @ NGT or PGT depending on the device
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