# D Flip-Flops: Design a counting circuit

Discussion in 'Homework Help' started by Treepton, Jul 14, 2014.

1. ### Treepton Thread Starter New Member

Jul 14, 2014
1
0
"Using 3 D flip-flops, design a circuit that will count out the sequence
0,7,4,5,6,3,2,1,0,  on each rising clock edge. Your circuit will have a clock
input and 3 output bits Q2,Q1,Q0"

I'm having trouble figuring out how to set this up. I know I need to create a truth table with Q2,Q1,Q0 and find Q2+,Q1+,Q0+, but from the examples I'm looking at, I can't figure out where the Q2+,Q1+,Q0+ values are coming from.

Any help would be appreciated, and thanks in advance!

2. ### MrChips Moderator

Oct 2, 2009
12,636
3,454
Designing a finite state machine is a classic class exercise in sequential logic design.

Create a truth table consisting of all eight states of Q2, Q1, Q0.

 Q2 Q1 Q0 Q2+ Q1+ Q0+ 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 0 1 1 1 0 1 1 1

Write down in the columns to the right the values of Q2+ Q1+ Q0+
where Q2+ Q1+ Q0+ is the next state after one clock pulse.

For example, 4 -> 5 as shown above.

After that, you have to draw three Karnaugh maps, one each for Q2+, Q1+ and Q0+.

Last edited: Jul 14, 2014
3. ### tshuck Well-Known Member

Oct 18, 2012
3,531
675
The Q2+,Q1+, and Q0+ come from your desired count sequence. Fill out the truth table MrChips provided for the current count (Q2,Q1,Q0 ) and what the next count (Q2+,Q1+,Q0+) should be for each count state.