D flip flop

Discussion in 'General Electronics Chat' started by armel, Feb 16, 2012.

  1. armel

    Thread Starter New Member

    Feb 16, 2012
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    hello

    i want to create a 4 digit keypad with D flip flop using quartus software can some one help?
    Thank
     
  2. Brownout

    Well-Known Member

    Jan 10, 2012
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    998
    You can't create a keypad with quartus software. First, you have to design your project. Then, you enter your design into quartus, which synthesises, maps and places your design. Then, you use quatus programmer to configure your FPGA.
     
  3. armel

    Thread Starter New Member

    Feb 16, 2012
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    0
    is it any way i can design the keypad with the D fip flop




    This is what i created the first 4input are acted as a keypad and i what to improve it with something that will have a delay so that any time that the first 4inputs are on position “1”; if any of the other input is on position “1” we can have a delay before have a “1” on the output.
    the rest of the circuit act as an alarm system when the first 4input are on “1” mean alarm set if any other input goes high 1 mean intruder in the system and output goes high to.
     
  4. armel

    Thread Starter New Member

    Feb 16, 2012
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    how could i introduce a delay on the output of a desing? i am using altera quartus 2 (cyclone2)
     
  5. Essadaoui_Red

    New Member

    Feb 17, 2012
    13
    1
    hello,
    try this

    LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    ENTITY delay IS

    PORT (a,b : IN std_logic;
    z : OUT std_logic
    );
    END delay;

    ARCHITECTURE behavior OF delay ISBEGIN
    dly0: PROCESS(a,b)
    BEGINz <= a NOR b AFTER 500 ns; -- delay 500 ns

    END PROCESS dly0;
    END behavior;


    ok good luck :)
     
    armel likes this.
  6. armel

    Thread Starter New Member

    Feb 16, 2012
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    i have attach my design. i want to add a delay on the input or output. is it anyways to do it schematicly?
    Thanks
     
  7. kubeek

    AAC Fanatic!

    Sep 20, 2005
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    i think this isn't synthesizable and will only work in simulation.
     
  8. kubeek

    AAC Fanatic!

    Sep 20, 2005
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    If you want a delay, you need a clock and a counter. There is no other way in fpga.

    Except maybe for delay locked loops which are used for clock buses, but this is for delays in the ns range, which I presume is way shorter than you want.
     
  9. Essadaoui_Red

    New Member

    Feb 17, 2012
    13
    1
    hello,
    isn't synthesizable :confused:
    can you say me please where is the problem??
    and give us an exemple of program with clock and counter !
    thank you :)
     
  10. kubeek

    AAC Fanatic!

    Sep 20, 2005
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    Look here on a basic VHDL rundown, and especially here.
    I hope you know that an FPGA basicly consists of lots of cells like this which consist of lookup tables and D flip-flops, and those cells are connected together like a mesh.

    BEGINz <= a NOR b AFTER 500 ns;
    tells the simulator to wait 500ns before setting that signal. You can't simply tell to a bunch of flip-flops to create and exact delay. Synthesizable means that the code you wrote can be implemented using the basic cells, so AFTER x ns is not synthesizable.
     
  11. kubeek

    AAC Fanatic!

    Sep 20, 2005
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    The FPGA allways has some external clock and runs on a certain frequency, typically 50MHz, that is clock period of 20ns. Let's say you want a delay of 1ms, so you need to use a counter and count to 1ms/20ns, that is 50,000 clock cycles.

    You could also make another clock derived from the main clock, say dividing it by 1000, so that the new clock runs on 50kHz, then you would count to just 50 clock cycles.
     
  12. armel

    Thread Starter New Member

    Feb 16, 2012
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    would it be a schematic counter and how would i set the cloc since i am using quartus software and i am testing it using the altera DE2 boad.
     
  13. kubeek

    AAC Fanatic!

    Sep 20, 2005
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    You should be able to find a counter in the schematic editor.
    I never used this software, but on xilinx the clock was available on one of the pins of the fpga, you will need to consult the manual from your board where to find it. Or your teacher.
     
  14. armel

    Thread Starter New Member

    Feb 16, 2012
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    please how can i derived a clock from the main one and how can design it. i am new on using quartus and sorry to ask to many question but i would appreciated your help
    Thanks
     
  15. kubeek

    AAC Fanatic!

    Sep 20, 2005
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    Ok, so lets say you have a 10-bit counter. Each input pulse adds 1 to the old value. So you count 0, 1 ,2 .. 1000. Each time you increment the value you also compare the value with 1000, and when the value matches you reset the counter to 0 and ouputput a pulse. This way you get one output pulse for every 1000 input pulses, so you basically divide the input frequency by 1000.
     
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