I want to write verilog code throw the function table given below


D C Q Qn
-------
0 0 Q Qn
1 ↑ 1 0
0 1 Q Qn
1 ↓ Q Qn

where D, c are input and Q and Qn are output

I am trying to write code
syncronous D flip flop with positive edge

 module D_flop (D,C,Q,Qn);
           Input D;
           input C;
           output Q;
           output Qn;
           Reg Q;
           Reg Qn;
           always @(posedge clk)
           initial

Don't know how to write next code

 

Don't use "initial" for this code. It's only good for testbench coding. now, you have an "always" block, but you need "begin" and "end" statements. within those two statements is where your flip-flop will get its functionality. You'll use basic assignmnet statements for this eg. Q <= D, and so forth.

 

You are missing a few possibilities in that table, for example what happens when this happens on the inputs
D C Q Qn
-------
0 ↑

 

You are missing a few possibilities in that table, for example what happens when this happens on the inputs
D C Q Qn
-------
0 ↑

ok you mean like this



D C Q Qn
-------
0 0 Q Qn
1 ↑ 1 0
0 1 Q Qn
0 ↑ 0 1
1 ↓ Q Qn

 

Don't use "initial" for this code. It's only good for testbench coding. now, you have an "always" block, but you need "begin" and "end" statements. within those two statements is where your flip-flop will get its functionality. You'll use basic assignmnet statements for this eg. Q <= D, and so forth.

now the code will be

module D_flop (D,C,Q,Qn); 
Input D; input C;
 output Q; 
output Qn; 
Reg Q; 
Reg Qn; 
always @(posedge clk) 
begin
If( ? )
Q <=....
else
Q <=......?
end
End module

how to complete code

 

Have you worked through any basic Verilog tutorials? This is usually one of the basic circuits that is covered.

 

now the code will be

module D_flop (D,C,Q,Qn); 
Input D; input C;
 output Q; 
output Qn; 
Reg Q; 
Reg Qn; 
always @(posedge clk) 
begin
If( ? )
Q <=....
else
Q <=......?
end
End module

how to complete code

Between the "begin" and "end" statements for the always block, the assignments are already sensitive to the rising edge of the clock signal. So, now all you need to do is just make the assignments straight from your table. The if(?) is not needed.

 

Between the "begin" and "end" statements for the always block, the assignments are already sensitive to the rising edge of the clock signal. So, now all you need to do is just make the assignments straight from your table. The if(?) is not needed.

ok I try to write code

module D_flop (D,C,Q,Qn); 
 Input D;
 input C; 
 output Q; 
 output Qn; 
 Reg Q; 
 Reg Qn; 
 always @(posedge clk) 
 begin 
 If( clock raise ) 
 Q <= 1'bo, 0'b1;
 else 
 Q <= Q 
 end
 End module

 

how about this

module D_flop (D,C,Q,Qn); 
 Input D;
 input C; 
 output Q; 
 output Qn; 
 Reg Q; 
 Reg Qn; 
 always @(posedge C) 
 begin 
 Q <= D;
 Qn <= !D; 
 end
 End module

 

how about this

module D_flop (D,C,Q,Qn); 
 Input D;
 input C; 
 output Q; 
 output Qn; 
 Reg Q; 
 Reg Qn; 
 always @(posedge C) 
 begin 
 Q <= D;
 Qn <= !D; 
 end
 End module

I think I have to write binary statement like if clock is raise then store the value 0 , 1 otherwise no change

 

no you don´t. The raising clock edge is taken care of by the "always @(posedge C)" so the block is executed anytime there is positive edge on wire C.
Now since your fuction table assigns 0 to Q when D is 0 and 1 when D is 1 it is as simple as assigning the value of
D to Q and the negative value to Qn: Q <= D;
Because Q and Qn are register types, they will remeber their value until you assign a new one.

 

no you don´t. The raising clock edge is taken care of by the "always @(posedge C)" so the block is executed anytime there is positive edge on wire C.
Now since your fuction table assigns 0 to Q when D is 0 and 1 when D is 1 it is as simple as assigning the value of
D to Q and the negative value to Qn: Q <= D;
Because Q and Qn are register types, they will remeber their value until you assign a new one.

I have complied that code on quartus software but there is some error

 

I have complied that code on quartus software but there is some error

Some error, are you serious? Have you thought about telling us WHAT that error was?

 

I have complied that code on quartus software but there is some error

Have you fixed the capitalization shown in the posted code? Verilog is case-sensitive.

You need to help people help you.

 

Some error, are you serious? Have you thought about telling us WHAT that error was?

Error (10170): Verilog HDL syntax error at D_flop.v(13) near text "module"; expecting ".", or an identifier ("module" is a reserved keyword ), or "(", or "["Error: Quartus II Full Compilation was unsuccessful. 3 errors, 0 warnings

 

End module should be "endmodule" -it needs to be run together(no space)...

 

End module should be "endmodule" -it needs to be run together(no space)...

I tried but there is same error

 

I tried but there is same error

Okay, how about you post the exact Verilog you've got and a screenshot of the errors...

 

Error (10170): Verilog HDL syntax error at D_flop.v(13) near text "module"; expecting ".", or an identifier ("module" is a reserved keyword ), or "(", or "["Error: Quartus II Full Compilation was unsuccessful. 3 errors, 0 warnings

obviously you are posting here just one error out of three. Please post all you´ve got, just like tshuck askes you to do.