D flip flop verilog code

Discussion in 'Programmer's Corner' started by vead, Jan 13, 2014.

  1. vead

    Thread Starter Active Member

    Nov 24, 2011
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    I want to write verilog code throw the function table given below


    D C Q Qn
    -------
    0 0 Q Qn
    1 ↑ 1 0
    0 1 Q Qn
    1 ↓ Q Qn

    where D, c are input and Q and Qn are output

    I am trying to write code
    syncronous D flip flop with positive edge
    Code ( (Unknown Language)):
    1.  module D_flop (D,C,Q,Qn);
    2.            Input D;
    3.            input C;
    4.            output Q;
    5.            output Qn;
    6.            Reg Q;
    7.            Reg Qn;
    8.            always @(posedge clk)
    9.            initial  
    Don't know how to write next code
     
  2. Brownout

    Well-Known Member

    Jan 10, 2012
    2,375
    998
    Don't use "initial" for this code. It's only good for testbench coding. now, you have an "always" block, but you need "begin" and "end" statements. within those two statements is where your flip-flop will get its functionality. You'll use basic assignmnet statements for this eg. Q <= D, and so forth.
     
  3. kubeek

    AAC Fanatic!

    Sep 20, 2005
    4,670
    804
    You are missing a few possibilities in that table, for example what happens when this happens on the inputs
    D C Q Qn
    -------
    0 ↑
     
  4. vead

    Thread Starter Active Member

    Nov 24, 2011
    621
    8
    ok you mean like this



    D C Q Qn
    -------
    0 0 Q Qn
    1 ↑ 1 0
    0 1 Q Qn
    0 ↑ 0 1
    1 ↓ Q Qn
     
  5. vead

    Thread Starter Active Member

    Nov 24, 2011
    621
    8
    now the code will be

    Code ( (Unknown Language)):
    1.  
    2. module D_flop (D,C,Q,Qn);
    3. Input D; input C;
    4.  output Q;
    5. output Qn;
    6. Reg Q;
    7. Reg Qn;
    8. always @(posedge clk)
    9. begin
    10. If( ? )
    11. Q <=....
    12. else
    13. Q <=......?
    14. end
    15. End module
    16.  
    17.  
    18.  
    how to complete code
     
  6. WBahn

    Moderator

    Mar 31, 2012
    17,743
    4,790
    Have you worked through any basic Verilog tutorials? This is usually one of the basic circuits that is covered.
     
  7. Brownout

    Well-Known Member

    Jan 10, 2012
    2,375
    998
    Between the "begin" and "end" statements for the always block, the assignments are already sensitive to the rising edge of the clock signal. So, now all you need to do is just make the assignments straight from your table. The if(?) is not needed.
     
  8. vead

    Thread Starter Active Member

    Nov 24, 2011
    621
    8
    ok I try to write code
    Code ( (Unknown Language)):
    1.  
    2. module D_flop (D,C,Q,Qn);
    3.  Input D;
    4.  input C;
    5.  output Q;
    6.  output Qn;
    7.  Reg Q;
    8.  Reg Qn;
    9.  always @(posedge clk)
    10.  begin
    11.  If( clock raise )
    12.  Q <= 1'bo, 0'b1;
    13.  else
    14.  Q <= Q
    15.  end
    16.  End module
     
    Last edited: Jan 14, 2014
  9. kubeek

    AAC Fanatic!

    Sep 20, 2005
    4,670
    804
    how about this
    Code ( (Unknown Language)):
    1.  
    2. module D_flop (D,C,Q,Qn);
    3.  Input D;
    4.  input C;
    5.  output Q;
    6.  output Qn;
    7.  Reg Q;
    8.  Reg Qn;
    9.  always @(posedge C)
    10.  begin
    11.  Q <= D;
    12.  Qn <= !D;
    13.  end
    14.  End module
     
  10. vead

    Thread Starter Active Member

    Nov 24, 2011
    621
    8

    I think I have to write binary statement like if clock is raise then store the value 0 , 1 otherwise no change
     
  11. kubeek

    AAC Fanatic!

    Sep 20, 2005
    4,670
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    no you don´t. The raising clock edge is taken care of by the "always @(posedge C)" so the block is executed anytime there is positive edge on wire C.
    Now since your fuction table assigns 0 to Q when D is 0 and 1 when D is 1 it is as simple as assigning the value of
    D to Q and the negative value to Qn: Q <= D;
    Because Q and Qn are register types, they will remeber their value until you assign a new one.
     
  12. vead

    Thread Starter Active Member

    Nov 24, 2011
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    I have complied that code on quartus software but there is some error
     
  13. kubeek

    AAC Fanatic!

    Sep 20, 2005
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    Some error, are you serious? Have you thought about telling us WHAT that error was?
     
  14. tshuck

    Well-Known Member

    Oct 18, 2012
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    Have you fixed the capitalization shown in the posted code? Verilog is case-sensitive.

    You need to help people help you.
     
  15. vead

    Thread Starter Active Member

    Nov 24, 2011
    621
    8
    Error (10170): Verilog HDL syntax error at D_flop.v(13) near text "module"; expecting ".", or an identifier ("module" is a reserved keyword ), or "(", or "["Error: Quartus II Full Compilation was unsuccessful. 3 errors, 0 warnings
     
  16. tshuck

    Well-Known Member

    Oct 18, 2012
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    End module should be "endmodule" -it needs to be run together(no space)...
     
    Last edited: Jan 14, 2014
  17. vead

    Thread Starter Active Member

    Nov 24, 2011
    621
    8
    I tried but there is same error
     
  18. tshuck

    Well-Known Member

    Oct 18, 2012
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    Okay, how about you post the exact Verilog you've got and a screenshot of the errors...
     
  19. kubeek

    AAC Fanatic!

    Sep 20, 2005
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    obviously you are posting here just one error out of three. Please post all you´ve got, just like tshuck askes you to do.
     
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