D flip flop function table

Discussion in 'General Electronics Chat' started by vead, Jan 10, 2014.

  1. vead

    Thread Starter Active Member

    Nov 24, 2011
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    help me to understand function table of D flip flop
    ^ = clock is raising
    _ = clock is falling
    when clock is raising then the value of Qn will be same as input D

    D Clk Qn

    0 ^ 0 clock raising so Qn will be same as input D
    1 ^ 1 clock raising so Qn will besame as input D
    X _ ? don't know the value of Qn when clock is falling


    can anyone explain last line
    IF D = 0 and clock is falling what will be Qn
    IF D =1 and Clock is falling what will be Qn
     
  2. ScottWang

    Moderator

    Aug 23, 2012
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    The symble for clock.
    v = clock is falling
    or
    ↑= clock is raising
    ↓= clock is falling

    D Clk Qn /Qn
    X --↓ Qn /Qn - The output values of Qn and /Qn are the same when clock is falling

    IF D = 0 and clock is falling then the Qn will be 0, it means that there is no change.

    IF D = 1 and Clock is falling then the Qn will be 1, it means that there is no change.

    Because The Qn of the D flip-flip will be actived when the clock is on the raising edge, so when the clock on the falling edge there is nothing to change.
     
  3. vead

    Thread Starter Active Member

    Nov 24, 2011
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    I think when clock is running there may be only two case means clock is raising or clock is falling or we can say clock is high or clock is low or clock high =1 and clock low =o


    IS this table is correct

    D c Qn
    0 ↓ 0
    0 ↑ 0
    1 ↓ 1
    1 ↑ 1
     
  4. t06afre

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    May 11, 2009
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  5. ScottWang

    Moderator

    Aug 23, 2012
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    The answer of table is right.

    Your memory method should be only in one condition is more easier, that is : The Qn of the D flip-flip will be actived when the clock is at the raising edge, the actived means that the Qn will be equal to input D, and the /Qn is the inverting of Qn, and don't care the others.

    The clock has 4 situations as : Low,↑,Hi,↓,...,Low,↑,Hi,↓,...
    ..__...__
    _↑..↓_↑..↓
     
  6. vead

    Thread Starter Active Member

    Nov 24, 2011
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    I know when clock is raising Qn will be same as input D
    D Clk |Qn
    --------------
    0 0 | ?
    1 0 | ?
    0 1 | ?
    1 1 | ?
    0 ↑ | 0
    1 ↑ | 1

    how to find out the value of Qn when clock is high or clock is low

    can you explain with truth table I tried lot but still I didn't understood
     
    Last edited: Jan 11, 2014
  7. ScottWang

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    Aug 23, 2012
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    You still don't get what I means - don't care the others (other conditions).

    Beside the clock at the ↑ raising time, the other conditions won't affecting the output of Qn and /Qn.
     
  8. kubeek

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    Sep 20, 2005
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    This is the sort of way this is written, Q(n-1) meaning the previous value of Q

    D Clk |Qn
    --------------
    0 0 | Qn-1
    1 0 | Qn-1
    0 1 | Qn-1
    1 1 | Qn-1
    0 ↓ | Qn-1
    1 ↓ | Qn-1
    0 ↑ | 0
    1 ↑ | 1

    But since the flipflop is triggered on positive edge, you really don´t need to show the rest of the cases apart from the two on the rising edge.
     
  9. vead

    Thread Starter Active Member

    Nov 24, 2011
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    I want to table in terms of 0s and 1s so help me to complete table in terms of 0s and 1s
     
  10. Brownout

    Well-Known Member

    Jan 10, 2012
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    It's not possible to complete your table in only terms of 1's and 0's. Flip-flops are a form of memory and are activated on rising edge of the clock. And so, at all other times (eg. falling clock edge) the output is the same as the value of the input at the last rising clock edge.
     
    kubeek likes this.
  11. vead

    Thread Starter Active Member

    Nov 24, 2011
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    it means that we can't create truth table in terms of 0s and 1s when clock is high,low or falling we can create only when clock is raising
     
  12. kubeek

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    Sep 20, 2005
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    Well yes, because the flipflop does nothing except when the clock is rising. Normally you wouldn´t even mention the rest of the cases.
     
  13. vead

    Thread Starter Active Member

    Nov 24, 2011
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    what does it mean
    there are also two input set and clear why we use please explain little bit
     
  14. t06afre

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    May 11, 2009
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    This table is quite representative. It covers it all. Since you are a student. I would suggest a visit to the school library. It often helps to browse more than book in the learning process
     
  15. kubeek

    AAC Fanatic!

    Sep 20, 2005
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    expanding on what t06afre posted, set and clear are usually asynchronous, meaning that the output will change regardless of clock.
    In the example the Clear signal is active low, that is when it is low the Q output will be "cleared" or set to 0.

    The Preset signal is the same thing, but it sets the Q output to 1.
     
  16. saraswathi.95

    Member

    Apr 11, 2013
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    we select flip flop at least to be stable for 1 clock period of time (as per our required task say processor requirement),hence flip flop is made enabled only at edge using a logic (A.Acompliment ,(.)refers to and operation and a is clock signal).hence truth table is as follows:

    D Q(n+1) {it refers to next state for the given input}
    0 0
    1 1

    and this happens when clock is at -ve edge for negative triggered and when +ve edge for positive triggered
     
  17. vead

    Thread Starter Active Member

    Nov 24, 2011
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    it means we don't need set reset in synchronous D flip flop
     
    Last edited: Jan 12, 2014
  18. kubeek

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    Sep 20, 2005
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    i think your missing the point here, the way the D input moves to Q output is snychronous with the clock. The set and reset inputs are asynchronous so the set or reset the output regardless of the clock.
    Every D flipflop is synchronous - its output reacts to the D input according to the clock, but some have the added feature of asynchronous reset and set inputs.

    (An R-S latch would be called asynchronous since it has no clock input)
     
  19. ScottWang

    Moderator

    Aug 23, 2012
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    Set and reset are the priority control pins, their priority are over D and clock.

    You can only using set and reset pins as a RS latch, you just ignore the D an clock, and connecting them to GND.
     
  20. vead

    Thread Starter Active Member

    Nov 24, 2011
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    th
    there are two type of flip flop asynchronous and synchronous flip flop
    synchronous flip flop we need clock cycle like flip flop with positive edge
    asynchronous with clock enable like D latch
     
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