Hi, anyone have some experience design flip flop in ltspice? Currently Im trying to design a flip-flop in ltspice unfortunately the output is not what I want
This is my design, for the transistors I'm using 45nm model : PMOS (l=45n, W=180n) NMOS (l=45n, 90n)
Parameters:
Vdd : 1.9v
clk : pulse wave with period 10ms
Output
the flip-flop triggered at both rising edge and falling edge, this is my first time using spice to design digital logics, any suggestions on what should i play around with in here. Thank you in advance
This is my design, for the transistors I'm using 45nm model : PMOS (l=45n, W=180n) NMOS (l=45n, 90n)
Parameters:
Vdd : 1.9v
clk : pulse wave with period 10ms
Output
the flip-flop triggered at both rising edge and falling edge, this is my first time using spice to design digital logics, any suggestions on what should i play around with in here. Thank you in advance