# D flip flop Behavioral Modeling

Discussion in 'Programmer's Corner' started by vead, Jan 17, 2014.

Nov 24, 2011
621
8
verilog code for d flip flop with positive edge
Code ( (Unknown Language)):
1. module d_ff( q, q_bar,d, clk);
2. input d ,clk;
3. output q,q_bar;
4. reg q,q_bar;
5. always@ (posedge clk)
6. begin
7. q <= d;
8. q_bar <= !d;
9. end
10. endmodule

q <=1'b0;
q_bar <=1'b1

what does it mean

2. ### tshuck Well-Known Member

Oct 18, 2012
3,531
675
Code ( (Unknown Language)):
1. q <=1'b0;
This assigns a 0 to the output signal 'q'.

Code ( (Unknown Language)):
1. q_bar <=1'b1
This assigns a 1 to the output signal 'q_bar '.

Now, If you place that into an always block with the sensitivity list being the posedge od a clock, then these assignments will take place at the positive edge of the clock.

Here are some comments to help out a little in your understanding
Code ( (Unknown Language)):
1. module d_ff( q, q_bar,d, clk);
2. input d ,clk;
3. output q,q_bar;
4. reg q,q_bar; // make q and q_bar register types
5.
6. always@ (posedge clk) // do the following when the positive edge of 'clk' comes.
7. begin
8.     q <= d; // assign(non-blocking) d to q on the positive edge of the clock(clk)
9.     q_bar <= !d; //assign(non-blocking) inverse of d to q on the positive edge of the clock(clk)
10. //Note: these assignments happen concurrently at the positive edge of the clock.
11. end
12. endmodule

Nov 24, 2011
621
8

ok thanks for replay

D flip flop function table

d clk q q_bar
0 ↑ 0 1
1 ↑ 1 0
0 ↑ 0 1
1 ↑ 1 0

now I want to write assign statement for this table

q <= 1b'0
Q_bar <= 1'b1
q <= 1b'1
q_bar <= 1b'0
q <= 1b'0
Q_bar <= 1'b1

is it correct ?

4. ### tshuck Well-Known Member

Oct 18, 2012
3,531
675
Your table is repeating itself, but yes, this is the correct functionality.

Note that the D flip-flop is referred to as the "delay" flip flop, meaning the output will be the input delayed by one clock cycle. Or, to look at it another way, the current state of D determines the state of Q at the next sensitive clock edge (e.g. Positive edge).

All that is to say that what you assign to Q should rely on D.

Your assignments, as they are, won't do anything - you have multiple, conflicting drivers for q and q_bar. If you want to do it that way, you need to test D and use its value to determine what is assigned to q/q_bar.

5. ### tshuck Well-Known Member

Oct 18, 2012
3,531
675
No. Remember, q is dependent on what d was before the clock edge. This means d must influence what q becomes, with q_bar simply being !q.

The stuff inside the always block is executed concurrently, so you cannot drive the same signal to two different states at the same time.

Yes, this is more like it.

This its what a flip-flop does.

Nov 24, 2011
621
8
Code ( (Unknown Language)):
1.
2. module d_ff( q, q_bar,d, clk);
3. input d ,clk;
4. output q,q_bar;
5. reg q,q_bar;
6. always@ (posedge clk)
7.  begin
8. q <= 1b'0
9. Q_bar <= 1'b1
10. q <= 1b'1
11. q_bar <= 1b'
12.  end
13. endmodule
14.
D flip flop table
d clk q q_bar
0 ↑ 0 1
1 ↑ 1 0

I want to ask the table and code i have posted is true for synchronous D flip flop with positive edge

7. ### tshuck Well-Known Member

Oct 18, 2012
3,531
675
Did you delete your previous post and repost it with slightly different wording?

Anyway, you seem a little confused about how to use the always block, see this page to get some more insight.