Hey guys. I have something I want to do with a DFF (7474) but I am not sure how to actually do it. First, I would like the output, Q, to be high all the time, which is going to be the control line of a tri state buffer. Is there a way I can pull the CLK to Vdd via a resistor so it is always high?

I then want to trigger the CRL with a low, so the output Q clears then returns high again once CLK gets a trigger.

Is this possible? THe problem I am having is how do I hold the output Q high before it receives any pulse from CLK?

 

There is an explicit SET input (pins 4 and 10) that are independent of the clock. You might want to have the D input pulled high if you control the clock. Use a 4.7K resistor for the pullup.

I can't translate the "CRL" input, unless you mean CLR.

 

I am sorry, I ment to say CLR. Ok so I pulled the D input high with a resistor. Now When I pulse CLR low, the output Q goes low as it should. Then when I pulse the CLK low, the Q output goes back high, but not when I pulse it high. Is this correct? I though Q takes on D input on the rising Clock, not a low pulse. Thoughts?

 

double check your data sheet for edge sensitivity. If it's falling edge sensitive, you could invert your clock as a last resort.

 

The 7474 clocks on the falling edge.

 

The 7474 clocks on the falling edge.

Annn..h! Sorry, but it is rising edge for the 7474!

 

well make a search on this topic in google search bar or you can read a e-book of digital electronics by M.Morris Mano