D Clocked Flip Flip

Discussion in 'Homework Help' started by hitmen, Mar 26, 2009.

  1. hitmen

    Thread Starter Active Member

    Sep 21, 2008
    159
    0
    For a D clocked flip, I know that D must be high before the clock goes high. (assuming PGT). However, what will happen if they are both triggered high at the same time?
     
  2. t_n_k

    AAC Fanatic!

    Mar 6, 2009
    5,448
    782
    There are two critical times "set-up, tsu" and "hold", thold. If not met then expected output change is not guaranteed. There is also a minimum clock pulse low width requirement for a maximum clock frequency.

    tsu - the time the D input must have been stable & high (or low) before the clock input 50% low-high transition point. For the HEF4013B Dual D type - CMOS Family - this is quoted (the one manuf. by Philips) as at least 40ns at 5V VDD.

    thold - the time the D input must remain stable & high (or low) after the clock input 50% low-high transition point. For the same chip this is at least 20ns at 5V VDD.

    Hope that helps.
     
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