D algoritham for testability circuit

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vead

Joined Nov 24, 2011
629
I need little help to understand following circuit


I don't understand image b and c

look at image b , D=0/1 where 1 represent good circuit and 0 represent bad circuit

why does A become 1 ?

look at c diagram if input of inverter is 1 then output will be 0
and output of inverter will become input for nand gate but here we know only one input of nand gate how we will determine another input
 

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timwhite

Joined Apr 10, 2014
50
"1. Choose a Fault." The entire purpose of this diagram is to work your way through a fault. In (a) they chose a fault at U2, being a 0 going into the input of the U3 gate. Then, at (b) they ask "What would cause this to be a 0," and work their way back through the inverter to the input.

Hope that helps as just a direct answer to your question.
 
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