The main idea behind current mirrors is that the output transistor behaves just like a VCCS (Vbe control current source). So by changing Vbe we change (set) Ic current. ...........
Because the only things that matters here is Vbe vs Ic characteristic.
And the first transistor (diode) job is to convert this input current into Vin (Vbe) voltage and nothing more.

Thank you Jony for pointing again to this fact because there is a common misconception (including KrisBlueNZ, see his post#38) that the BJT would be a CCCS.

 

Thank you Jony for pointing again to this fact because there is a common misconception (including KrisBlueNZ, see his post#38) that the BJT would be a CCCS.

I did describe it that way in my earlier posts (not post #38 though, as far as I can see). But it is a common misconception - the tutorial at http://www.allaboutcircuits.com/vol_3/chpt_4/14.html only mentions the base-emitter voltage to explain that the equal voltages cause equal base currents.

 

The role of Vce and the Early Effect should not be overlooked. Playing with a couple of different transistor types I noticed some quite substantial changes in Ic when going from the diode configured mode to the case of Vce set to 5V. The Vbe voltage was kept constant for both conditions, starting with Vbe adjusted to give 1mA in the diode connected mode. There seemed to be a strong link to β. I plan to do some more careful tests with my limited resources. Perhaps others can verify theses results.
The invention of the Wilson current mirror is obviously one solution to the Early Effect "problem".

@KrisBlueNZ. I wouldn't apologize for anything you've contributed thus far. Sure, you need to justify your "stand", but that's a different issue. And you've been quite civil in your comments, which is refreshing.

 

The role of Vce and the Early Effect should not be overlooked. Playing with a couple of different transistor types I noticed some quite substantial changes in Ic when going from the diode configured mode to the case of Vce set to 5V. The Vbe voltage was kept constant for both conditions, starting with Vbe adjusted to give 1mA in the diode connected mode. There seemed to be a strong link to β. I plan to do some more careful tests with my limited resources. Perhaps others can verify theses results.
The invention of the Wilson current mirror is obviously one solution to the Early Effect "problem".

@KrisBlueNZ. I wouldn't apologize for anything you've contributed thus far. Sure, you need to justify your "stand", but that's a different issue. And you've been quite civil in your comments, which is refreshing.

I agree, but first things first. Once the ideal basic current mirror is understood, then the next thing to examine and understand is the effect that the finite impedance (due to Early effect) has on performance and how significantly different the output current can be as a result. At about this same time some effort to examine the effect of parameter mismatch should be made. That then motivates the development of some better mirror topologies, including the Wilson mirror.

 

I agree, but first things first. Once the ideal basic current mirror is understood, then the next thing to examine and understand is the effect that the finite impedance (due to Early effect) has on performance and how significantly different the output current can be as a result. At about this same time some effort to examine the effect of parameter mismatch should be made. That then motivates the development of some better mirror topologies, including the Wilson mirror.

Thanks WBahn. I should have also noted your earlier reference to the Early Effect (pardon the pun).

I raised this because the recent comments seemed to suggest one only needed to match device fabrication and that was the end of the matter - which clearly it isn't.

 

We've been neglecting the Early effect, and any other imperfections.

Regarding the Early effect, Horowitz and Hill (2nd edition pp 89) say "In practice, the current might vary 25% or so over the output compliance range - much poorer performance than the current source with emitter resistor ...".

They don't say what output compliance range they have defined. Obviously as the output transistor approaches saturation, its current will drop and its impedance will be compromised. I guess they have defined the low-Vce end of the compliance range to exclude saturation, but I wonder where exactly they drew the line, and whether narrowing the expected compliance range would reduce the error much below 25%.

They describe the Early effect as a "slight variation of Vbe, " (not β) "with Vce (at a given Ic)". I guess the effect is the same; only the mechanism would be different.

 

We've been neglecting the Early effect, and any other imperfections.

Regarding the Early effect, Horowitz and Hill (2nd edition pp 89) say "In practice, the current might vary 25% or so over the output compliance range - much poorer performance than the current source with emitter resistor ...".

They don't say what output compliance range they have defined. Obviously as the output transistor approaches saturation, its current will drop and its impedance will be compromised. I guess they have defined the low-Vce end of the compliance range to exclude saturation, but I wonder where exactly they drew the line, and whether narrowing the expected compliance range would reduce the error much below 25%.

They describe the Early effect as a "slight variation of Vbe, " (not β) "with Vce (at a given Ic)". I guess the effect is the same; only the mechanism would be different.

Hopefully they have previously defined what they mean by "output compliance range". They may have done it quite some ways back. My guess is that it is the range of outputs that keeps the transistor in the active region.

While the descriptions may differ and may be equivalent, the mechansism is the mechansism -- the transistor doesn't give a hoot how it is described.

I believe a description involving a lowering of β as Vce increases is probably the closest to the actual mechansim, namely base-width modulation, responsible.

But describing it as needing a greater Vbe to achieve the same Ic is very useful from many applied perspectives.

But saying that it is a "slight" change in Vbe for the same Ic, while accurate, is arguably misleading because it belies the fact that slight changes in Vbe have major impacts on Ic. For instance, in most applications a doubling (or halving) of Ic would be seen as significant. But the ~20mV change in Vbe that corresponds to this might be seen as "slight".

The effect is quite significant.

 

Regarding the Early effect, Horowitz and Hill (2nd edition pp 89) say "In practice, the current might vary 25% or so over the output compliance range - much poorer performance than the current source with emitter resistor ...".

With regards to the use of emitter resistors, if you are using discrete transistors, then unless you KNOW they came from the same lot, you can be pretty much assured that they will have significant mismatches in their charactersitics. Even if they came off the same wafer, the mismatch from one side of the wafer to the other can be significant (though generally less than if they come from different wafers). So you would need to cherry pick them to find suitably matched transistors.

The classic current source configurations are really intended for IC designs.

The use of emitter resistors (what I tend to call ballast resistors) is a very effective way of removing the sensitivity to just about all variations in the transistors. Heck, you can use a small signal transistor and a power transistor and get very good matching between input and output current. About the only thing that matters is the difference between Vbe at the same emitter current and you can choose sufficiently large ballast resistors to make that difference negligible pretty easily.

 

Hopefully they have previously defined what they mean by "output compliance range". They may have done it quite some ways back.

From the start of the section on current mirrors, there's only "One nice feature of this circuit is voltage compliance of the output transistor current source to within a few tenths of a volt of VCC," (for a PNP circuit), "since there is no emitter resistor drop to contend with."

My guess is that it is the range of outputs that keeps the transistor in the active region.

How do you define the border between active region and saturation?

I believe a description involving a lowering of β as Vce increases is probably the closest to the actual mechansim, namely base-width modulation, responsible.

I thought the Early effect caused β to increase with increased Vce...?
It slopes in the same direction as the saturation curve.

But saying that it is a "slight" change in Vbe for the same Ic, while accurate, is arguably misleading because it belies the fact that slight changes in Vbe have major impacts on Ic.

Right.

 

The classic current source configurations are really intended for IC designs.

Or you can use a dual transistor or a matched transistor.

BTW, do you know what level of matching you can assume for a dual transistor such as the BC847BD (6-pin SMT device from ON Semi, Fairchild, NXP, Infineon)? (Confusingly, the dual transistor has the same base part number as the single version!)

The data sheet (from ON Semi) doesn't specify ANY matching parameters. By contrast, the MAT01, MAT03 and MAT14 devices from AD specify input offset and gain matching. They're described as matched transistors, and they cost over ten times as much as the dual transistors.

Can we make any assumptions about matching in a dual transistor?

The use of emitter resistors (what I tend to call ballast resistors) is a very effective way of removing the sensitivity to just about all variations in the transistors. Heck, you can use a small signal transistor and a power transistor and get very good matching between input and output current.

LOL

 

From the start of the section on current mirrors, there's only "One nice feature of this circuit is voltage compliance of the output transistor current source to within a few tenths of a volt of VCC," (for a PNP circuit), "since there is no emitter resistor drop to contend with."

The concept of "compliance" and "compliance range" are much more general than current mirrors. So you probably need to look in the sections where they talk about the behavior of the basic common-emitter circuits to find it.

How do you define the border between active region and saturation?

You can define it in a few different ways that are different but roughly comparable. The particular definition depends on what is important in the application being considered.

Often times it is simply defined as the point at which Vce=Vcesat where Vcesat may be something based on the datasheet or it may be a somewhat arbitrary voltage such as 0.25V or 0.5V. Some use a definition based on Vcb=0V. The goal in most cases is to keep the device sufficiently linear when it is in the active region -- and "sufficiently linear" is application specific.

I thought the Early effect caused β to increase with increased Vce...?
It slopes in the same direction as the saturation curve.

Right.

You are correct. My bad. I was visualizing the curves in my mind (at least I had those correct) but my mental manipulations when wrong somewhere along the way. Actually, I know where -- and it was a mental blunder owing to not keeping the axis parameters straight in my mind.

At a fixed Vbe, if you increase the Vce you get more collector current. As long as the base current doesn't go up by an equal amount, this is equivalent to an increase in β.

Thanks for catching the error and pointing it out.

 

Or you can use a dual transistor or a matched transistor.

I consider those ICs. But it could be argued either way.

Can we make any assumptions about matching in a dual transistor?

Don't really know. You'd have to rely on the manufactures documentation. The data sheet may or may not have it, but if it doesn't there is probably some higher level documention, such as for the family of products, or an app note or something that discusses it. The better vendors include references to such material in the data sheets, but many don't. You might wade through their website and find something.


BTW, I didn't really mean for my example of using a small signal transistor and a power transistor as being funny -- though I can see how it would be taken that way. I've actually used that very approach in a few testing situations. In one that I recall fairly well (talking a decade ago, so memory leaks come into play) was that I needed to be able to pull up to about 500mA total from a pin on an IC we were testing and we needed to be able to control it fairly well. So I rigged up a little circuit with a pot that let my control the current through a small signal transistor up to 50mA and put two 100Ω resistors in parallel as the ballast resistor for the programming transistor. Ideally, I would have put twenty of these same resistors in parallel for the ballast resistor for the power transistor I used as the image transistor, but I concluded that that was over kill. Instead I put four 20Ω 1W we had on hand in parallel. It worked extremely well (for the purpose at hand).

 

(Compliance)
You can define it in a few different ways that are different but roughly comparable. The particular definition depends on what is important in the application being considered.
Often times it is simply defined as the point at which Vce=Vcesat where Vcesat may be something based on the datasheet or it may be a somewhat arbitrary voltage such as 0.25V or 0.5V. Some use a definition based on Vcb=0V. The goal in most cases is to keep the device sufficiently linear when it is in the active region -- and "sufficiently linear" is application specific.

Right. I thought it might be defined as a point where the slope of the knee on the Ic vs. Vc graph reaches a particular angle, or a particular deviation from its angle in the active region.
Would it be right to categorise the Early effect as a "mild case" of saturation? In other words, are they caused by the same physical conditions inside the transistor? I don't suppose they are, but I wondered, since they have the same effect (β dropping as Vce drops).

At a fixed Vbe, if you increase the Vce you get more collector current. As long as the base current doesn't go up by an equal amount, this is equivalent to an increase in β.

Right. Just out of interest I simulated a 2N3904 with LTSpice, with a fixed Vbe. For a Vce range of 0.35V to 20V, and Ic ≈ 10 mA, Ib drops steadily from 33.57 µA to 33.34 µA (about 0.7%) as Vc rises. I don't know how accurate the model is, but that seems reasonable I think.

(Tracking of "dual" transistors)
Don't really know. You'd have to rely on the manufactures documentation. The data sheet may or may not have it, but if it doesn't there is probably some higher level documention, such as for the family of products, or an app note or something that discusses it. The better vendors include references to such material in the data sheets, but many don't. You might wade through their website and find something.

Good idea. I couldn't find any application notes for dual transistors on ON Semi, Fairchild, NXP nor Infineon. I guess we have to assume they aren't guaranteed to be matched at all :-(

(...) Ideally, I would have put twenty of these same resistors in parallel for the ballast resistor for the power transistor I used as the image transistor, but I concluded that that was over kill.

What do you mean "image" transistor?

 

Right. Just out of interest I simulated a 2N3904 with LTSpice, with a fixed Vbe. For a Vce range of 0.35V to 20V, and Ic ≈ 10 mA, Ib drops steadily from 33.57 µA to 33.34 µA (about 0.7%) as Vc rises. I don't know how accurate the model is, but that seems reasonable I think.

Therein lies one of the reasons some folks eschew simulations......

Consider a TO-92 2N3904 with Vce at 20V and ~10mA collector current. The collector dissipation is ~200mW. With a typical thermal resistance of 200K/W (junction to ambient) this would mean in rough terms a junction (die) temperature rise over the test cycle of the order of 40C. If the base-emitter junction temp varies by a similar range, then we could expect a Vbe drop of the order of 100mV [at -2.5mV per degree C rise for Si]. This would have far more dramatic consequences than are indicated by a simple simulation.

 

Would it be right to categorise the Early effect as a "mild case" of saturation? In other words, are they caused by the same physical conditions inside the transistor? I don't suppose they are, but I wondered, since they have the same effect (β dropping as Vce drops).

* EARLY-effect:
The amount of the Early effect (i.e the slope of the Ic=f(Vce) curve) is determined under the condition of constant Ib - not constant Vbe.
* Physical reason: A rising Vce causes an increase of the width of the depletion layer (between Cand B) and a corresponding width reduction of the B-E junction. This allows more collector current.

 

By connecting our diode to the base of the transistor, a small amount of the input current is diverted from the diode to feed the transistor base. This redirected current no longer goes through the diode and hence no longer participates in generating the needed Vbe across the diode. This results in a further slight mismatch between the input current and the output current.

A small amount of the input current is diverted from the diode to feed the transistor base..hence causing further slight mismatch…since we cannot totally cancel out this base current as this is necessary to on the transistor Q1 and Q2 though( it bring a slight mismatch)..so what would be the approximate value of this Ib ..should it be a compromise value that makes Iin participate up to its maximum extent in generating needed Vbe across the diode and on the other hand turn ON the transistor Q1 so that Iout could trace Iin equally..

 

Wrong Forum to discuss this. Feel free to open yourn own thread.