CS JFET amplifier design

Discussion in 'Homework Help' started by darylsingh, Jul 19, 2011.

  1. darylsingh

    Thread Starter New Member

    Jul 10, 2011
    15
    0
    I'm working on designing a CS JFET amplifier for class and wanted to make sure of a couple of equations: 1. Is IDSS assumed to be half of IDQ? 2. Is Vp assumed to be 1/3 of VGSQ? 3. And is VDD assumed to be half of VDSQ?
     
  2. lopoditi

    New Member

    Jul 24, 2011
    6
    1
    What is Vp?

    Vdd must be greater than Vdsq, since Vdd is the power supply.

    Idq = 0 (assuming q=quiescent)

    maybe clarify what your variables refer to, but these are my answers based on guesses about ur variables.
     
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