# creating a fast counter with low clock speed

Discussion in 'The Projects Forum' started by twistadias, Aug 17, 2008.

Aug 17, 2008
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Im required to build a digital tone generator using Quartus. Theres only one clockl input with a speed of 1Hz.

Now I most part of the tune plays fine on 1Hz but I want to speed up the certain parts. The clock is connected to a counter which counts upto 31.

Is there a way to increase the counter speed on those certain parts say from number 10 to 20. the counter is a set of positive edge triggered D flip-flops connected together.

I was planning to create another counter which counts faster but I dont know how?

I cannot add another input at a higher clock speed.

2. ### mik3 Senior Member

Feb 4, 2008
4,846
63
Firstly, you cant count faster unless you have a faster clock. If you want to count faster between 10-20 then make a circuit with logic gates to detect when you reach number 10, then this circuit will make your clock count faster or enable a second faster clock until it counts up to 20. Then the logic gates circuit will disable the fast clock and enable the slow clock and continue with counting.

It is better to use a microcontroller if you can, you save money and the circuit will be more compact.

3. ### beenthere Retired Moderator

Apr 20, 2004
15,815
282
Got any idea how the 1 Hz clock gets generated? It's very common to have a 1024 Hz oscillator somewhere and simply divide the frequency don to whatever lower freq you want.

If you have an oscillator somewhere, you might be able to grab a higher frequency from it for your faster clock. Having a schematic will give you that information, or you could also use an oscilloscope to trace the clock back to its source.

4. ### Papabravo Expert

Feb 24, 2006
10,135
1,786
The standard method of doing this is to use a phase locked loop. Assume you have a VCO (Voltage Controlled Oscillator). The output of this VCO is divided down by some factor like 10 or 20 and it is compared to your reference frequency(1 Hz.). Then you adjust the frequency of the VCO so that it has the same phase as the reference frequency.

Consider just the falling edges. If the divided VCO signal leads the reference then the VCO frequency is too high and needs to be lowered. If the reference leads the divided VCO then the VCO frequency is too low and the VCO frequency needs to be raised.

Clever Eh?

Aug 17, 2008
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huh? that went over my head.

My idea was to create a counter that counts on both the rising and falling edges of the clock. Then use some of these counters in series thereby creating a fast counter.

Is there any way to do this? Or is there a website related to this kind of stuff?

6. ### John Luciani Active Member

Apr 3, 2007
477
0
As was previously mentioned the phase-locked loop (PLL) is the circuit you want.
You place a divide-by-n counter in the feedback loop and your output frequency
is multiplied by a factor of N.

You should be able to do this with two ICs. Take a look at the 4046 IC. I believe that
TI, On-Semi, NXP and Fairchild still sell these. There are probably application notes
showing the divide-by-N counter. If you can make N a power of 2 (2,4,8,..) you can just
use a regular counter.

I believe "The CMOS Cookbook" by Don Lancaster has some PLL information.
For more detailed information checkout "Phaselock Techniques" by Floyd M. Gardner
ISBN 0471042943.

(* jcl *)

P.S. If you do the math for the loop filter your professor will probably give you extra
credit ;-)

Last edited by a moderator: Aug 19, 2008