Creating a delayed pulse, given a pulse train

Discussion in 'General Electronics Chat' started by drkblog, Oct 12, 2012.

  1. drkblog

    Thread Starter Member

    Oct 4, 2012
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    This may sound a little obvious, but even when I think of ways for doing this, I think there must be something simpler:

    I have a digital signal (a train pulse) lets say 200ms active 50ms passive. And I need to create another pulse of 5ms matching the last 5 ms of the passive period:

    Code ( (Unknown Language)):
    1.  
    2. Original
    3.  
    4. 200        50
    5. --------+      +---
    6.         |      |
    7.         +------+
    8.  
    9. Created
    10.                 5
    11.              +-+
    12.              | |
    13. -------------+ +---
    14.  
    What would be the simplest / cheaper way of doing this?
     
  2. praondevou

    AAC Fanatic!

    Jul 9, 2011
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    Any clock available? What precision do you need?

    If no clock is available and you don't need high precision you can use the falling edge of the 200ms to trigger a 555 monostable whose falling edge triggers a second 555 monostable (after 45ms).

    It depends on the delays necessary between the 200ms and 5ms edges etc to determine if this would be suitable. What is it used for? Where does the pulse train come from?
     
  3. drkblog

    Thread Starter Member

    Oct 4, 2012
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    No clock. The original train is from a 555 astable circuit. In fact it's a 556 so I could use the second timer for that.

    I need this for synchronizing a counter and a 7 segment display. During the low period (50ms) I have to count. Then I have to show the number in the display. I have /Latch and Reset controls. I could use the original signal for both controls. So the circuit would latch and reset during high, and show the counter and count during low. At some point that works, specially because the count time is short and the human eye is slow. But as the count time increases, the display will start going unstable, or difficult to read.

    I though the second (delayed) pulse would be useful for disable latching just over the end of the count time.
     
  4. MrChips

    Moderator

    Oct 2, 2009
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    I think you have the carriage before the horse.
    What you are trying to implement is a classic counter/display sequence which goes:

    reset - count - latch - reset ...

    Just design three timing signals to follow each other in sequence A-B-C and everything should fall into place.

    Note that the reset and latch pulses can be as short as 50ns and therefore might have negligible effect on your count accuracy.
     
  5. drkblog

    Thread Starter Member

    Oct 4, 2012
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    Well, that's the point. I have a sequence of two stages (original) and I want to build the three stages you mentioned. The question is what's the cheapest way. I have an astable timer and I can use a monostable as praondevou suggested. Which is what I'm going to do. Is there another way?
     
  6. THE_RB

    AAC Fanatic!

    Feb 11, 2008
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    This sounds like a typical repeating "random" number generator. The typical way is to run the oscillator and counter when the 555 output is HI, then when the 555 output goes LO it latches the count to the display.

    You need a 555 oscillator and the counter IC, then another 555 to do the "gating" task. You set up the display driver to latch on the 555 output \ edge.
     
  7. MrChips

    Moderator

    Oct 2, 2009
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    What you need is an edge triggered monostable. And the simplest way to implement a monostable is with a capacitor and a resistor.
     
  8. drkblog

    Thread Starter Member

    Oct 4, 2012
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    Well, I designed the circuit using the second timer of the LM556 as a monostable triggered in the negative edge of the main timer. That gives me the first two signals of this graphic. But I needed the third signal, which is a NOR of the other two:
    Code ( (Unknown Language)):
    1.  
    2. Main timer
    3.  
    4.  200ms       50ms
    5. ----------+        +-------
    6.           |        |
    7.           +--------+
    8.          
    9. Monostable
    10.             45ms
    11.           +-----+
    12.           |     |
    13. ----------+     +----------
    14.  
    15. Latch disable
    16.  
    17.             5ms
    18.                 +--+
    19.                 |  |
    20. ----------------+  +-------
    21.  
    So I built a NOR gate using two transistors and a couple of resistors. Is it a good idea to build gates using transistors (when you need only one gate)?
     
  9. MrChips

    Moderator

    Oct 2, 2009
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    I see nothing wrong with that. You should be able to do it with one transistor and some resistors.
     
  10. drkblog

    Thread Starter Member

    Oct 4, 2012
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    This is the signal I've got by conecting the Main timer and the monostable to the NOR gate built with the circuit on the right. In the oscilloscope you can see the NOR output in red and the main timer in green:

    [​IMG]

    I'm worried about the 2.3V level in the output when A is 5V and B is 0V...
     
    Last edited: Oct 13, 2012
  11. drkblog

    Thread Starter Member

    Oct 4, 2012
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    Problem solved simplifying the NOR circuit:

    [​IMG]
     
  12. timescope

    Member

    Dec 14, 2011
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    I would :
    1. Generate 4 times the frequency with a 555 square wave circuit ( R1<< R2 or with a
    diode across R2).
    2. Use a 4013 to divide by 4.
    3. Use gates like 4011,4001 etc to gate the 5 outputs to obtain the sequence.
    Timescope.
     
  13. drkblog

    Thread Starter Member

    Oct 4, 2012
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    In the end, I solved it using both timer of the LM556 and no gates at all. I created a timer at 2Hz (astable) and triggered the second timer (monostable for 50ms) upon negative edge of the first timer. Used the first one as the reset and the second one as the latch disable. And this worked.

    Of course latch is disabled during count time, but since it's only 50ms it isn't a problem. The solution I was trying to implement didn't worked because the counter reset takes place before latch is enabled. The right solutions would be using the enable signal of the counter too. But that circuit was being recycled and I didn't want to modify it.
     
    Last edited: Oct 14, 2012
  14. MrChips

    Moderator

    Oct 2, 2009
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  15. drkblog

    Thread Starter Member

    Oct 4, 2012
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    Nice! I used a similar circuit in a previous circuit (from the project I inherited the counter/latch/7-seg module). As you say, playing with capacitor values you can get the delay. In this case, as I was around 50ms I knew it wasn't going to be visible. And reduced the cost and the size of the circuit. Good enough for a prototype, I guess.
     
  16. takao21203

    Distinguished Member

    Apr 28, 2012
    3,577
    463
    A 16F54 could be used for this application.
    These simple controllers are meant to be to replace circuits based on several ICs, and additional discrete components.
     
  17. drkblog

    Thread Starter Member

    Oct 4, 2012
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    I guess a microcontroller is a little too much for something like this.
     
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