Creating a 3 bit counter using D Flip Flops

Discussion in 'Homework Help' started by Getts, Apr 20, 2014.

  1. Getts

    Thread Starter New Member

    Apr 12, 2014
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    So this guy pretty much has the same assignment as I do from what I can see.

    http://forum.allaboutcircuits.com/showthread.php?t=80257

    However, I have no clue what I'm doing. Been looking around on the forums and I can't make sense of most of what I see. I haven't really learned much about flip-flops yet so I'm having a hard time visualizing how it works exactly.

    But, I'm tasked with making a 3-bit and 5-bit counter out of D-Flip Flops and various logic gates. It's got the two inputs CE, and the clock. And two outputs which are either a 3 or 5-bit bus and a terminal counter which is 1 when all bits are 111 or 11111.

    I don't even know how to create the truth table for this function so I'm utterly in the dark here.

    Thanks
     
  2. ericgibbs

    AAC Fanatic!

    Jan 29, 2010
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    hi G,
    Before you consider designing a counter I would recommend you study a single D type F/F [ Bi-stable] and create the truth table, so that you understand the basic F/F operation.

    Post what you think the truth table is for a single F/F.
     
  3. Getts

    Thread Starter New Member

    Apr 12, 2014
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    Alright so I learned a LITTLE bit about it. However, the flip flops I used in lecture are slightly different from the ones I'm seeing in practice.

    Anyway,

    Q Q(+1) D
    0 0 0
    0 1 1
    1 0 0
    1 1 1

    Where Q and Q(+1) are the states, and D is the control bit.

    I've seen the timing diagram as well, and understand that. But I don't know how to get a counter from this set of information.
     
  4. ericgibbs

    AAC Fanatic!

    Jan 29, 2010
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    hi,
    OK, a visual representation of a divide by 2 F/F counter maybe easier for to understand.
    Look at this image, what is the relationship between the Clock [ck] and Q0.??
     
  5. Getts

    Thread Starter New Member

    Apr 12, 2014
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    So when the clk pulse changes, it causes the Qo to change for one cycle as well right?

    However, I don't understand why the Q' is fed back into D. Wouldn't that change every value of Qo?
     
  6. ericgibbs

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    Jan 29, 2010
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    hi,
    What is the frequency of Q0 compared to the Clock frequency.?
     
  7. Getts

    Thread Starter New Member

    Apr 12, 2014
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    Ah! The frequency of the Qo is double that of the Clocks.

    ...But I don't see how that helps exactly.
     
  8. Getts

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    Apr 12, 2014
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  9. JoeJester

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    Apr 26, 2005
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    You might want to rethink that. Freq = 1/period.
     
  10. Getts

    Thread Starter New Member

    Apr 12, 2014
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    Oh whoops, I wasn't thinking when I entered that I guess. The clock is double the frequency of the Qo.
     
  11. ericgibbs

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    Jan 29, 2010
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    So if we add another identical F/F stage, what will the final division ratio on Q1 of the 2nd F/F .??
     
  12. Getts

    Thread Starter New Member

    Apr 12, 2014
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    Q1 should be a fourth of the clock frequency right?

    Also, I finally got a truth table from class, which isn't actually turning out right for some reason.

    The final expressions I get for each input into D is D0, given the inputs Q2, Q1, Q0 and Counter Enable (CE) is
    D0=CE XOR Q0
    D1= Q1 XOR (CEQ0)
    D2= Q2 XOR (CE*Q0*Q1)

    This is my schematic for it, but when simulating, it doesn't actually count in order. I'm not 100% sure what's wrong.
     
  13. tshuck

    Well-Known Member

    Oct 18, 2012
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    You may want to give this a read - it was written to supplement the section of the eBook on synchronous counters.
     
  14. Getts

    Thread Starter New Member

    Apr 12, 2014
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    I was actually looking through that very thread the other day. It helped, but unfortunately I'm limited to D flip flops, and I actually have no clue how the JK-Flip flops work yet to be honest. I know they're a combination of T and D and that's about it.

    So I got another schematic that finally worked, however I have no idea why it does, since the book I pulled it from doesn't give me a corresponding truth table. And what also bothers me is why my other schematic DOESN'T work. I would type out the truth table for my schematic above, but I don't quite know how to format it so it doesn't come out a jumble of 1's and 0's.

    Here's what I have now.
     
    Last edited: Apr 21, 2014
  15. tshuck

    Well-Known Member

    Oct 18, 2012
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    The process is similar, but actually easier for D flip flops (there's only one input, as opposed to the two for a JK flip flop). What you are doing with the K-maps is, essentially, minimizing the logic that will provide the next count, given the current count - referred to as the input-forming logic.

    In other words, you determine what the next count will be, given the current count. This counter uses multiple flip flops, so you must determine the input-forming logic for each flip flop.

    This thread is a more advanced topic, but the same methodology is used to create a counter with D flip flops (disregard the other stuff for now, that just might serve to confuse you at this point). This is just to show how the K-maps might be arranged and the input-forming logic can be determined.
     
  16. WBahn

    Moderator

    Mar 31, 2012
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    You seem to be wanting to jump from Step 1 straight to Step 9.

    Slow down and take things one step at a time. The first thing is to clearly define what this counter should do for all possible combinations of state and inputs.

    First, explain in words what the circuit is supposed to do. I'll do this one for you so that you can see what I am getting at:

    Design a synchronous 3-bit binary counter that, in addition to the 3-bit output value, also has a Terminal Count (TC) output that is HI whenever all of the output bits are HI (i.e., when the count is 7). In addition to the clock input, there is a Count Enable (CE) input that permits normal counting when HI but inhibits counting (i.e., the count doesn't change) when LO. D-type flip flops (positive-edge triggered) are to be used.

    Now, we assume that the clock is a free running clock and so we don't need to include it explicitly in our tables and such as every transition is assumed to occur on a rising clock edge.

    The transition table for a D-type flip flop is

    Q D Q'
    0 0 0
    0 1 0
    1 0 1
    1 1 1


    Note that Q' means the next value of Q (as opposed to NOT(Q)).

    You had mentioned that you didn't know how to make a table. Quote this post and examine the TABLE code and you will see how you can make one.

    Notice that the current state is on the left of the table, the inputs are next, and the next state is on the right. If there are any outputs, they would appear next. This is a handy convention as it maps well to a state transition diagram. I've also included blank columns to separate the three groups.

    So now it's your turn. For your three bit counter name your states S0 through S7 (corresponding to bit patters 000 through 111) and complete the following table (note the addition of an output column for TC):

    S CE S' TC
    S0 0 ? ?
    S0 1 ? ?
    S1 0 ? ?
    S1 1 ? ?
    S2 0 ? ?
    S2 1 ? ?
    S3 0 ? ?
    S3 1 ? ?
    S4 0 ? ?
    S4 1 ? ?
    S5 0 ? ?
    S5 1 ? ?
    S6 0 ? ?
    S6 1 ? ?
    S7 0 ? ?
    S7 1 ? ?


    Once you have this correct, we can augment it with the values of the three flip flops and, after that, with the values that the D-inputs to the flop flops have to have. At that point you will be ready to look at K-maps, but not before.
     
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