CPLD Design - Schematic Vs VHDL efficiency

Discussion in 'Digital Circuit Design' started by Robin Mitchell, Sep 3, 2016.

  1. Robin Mitchell

    Thread Starter Well-Known Member

    Oct 25, 2009
    734
    200
    Hi all,

    So I am designing a mark II graphics card (320 x 200) on a CPLD (Xilinx 9572XL) and was wondering if a schematic is more or less "efficient" than VHDL. In other words, does a well designed schematic use fewer macrocells than VHDL?

    I know that schematics are converted into VHDL but is that VHDL more efficient that the user programmed VHDL?

    All the best,
    Robin
     
  2. Papabravo

    Expert

    Feb 24, 2006
    10,148
    1,791
    All mappings have problems depending on the macrocell architecture. You can of course design your schematic in such a way that it is relatively easier or harder for the software to do the mapping. Without running an experiment I'm not sure I would want to go out on a limb and predict the result one way or the other. We live in a world where the chips now have resources to burn regardless of the input methodology. Such questions come from a bygone era where one had to carefully allocate the available resources.
     
  3. Robin Mitchell

    Thread Starter Well-Known Member

    Oct 25, 2009
    734
    200
    @Papabravo

    The CPLD I am using is rather constrained and have managed to get the whole video processor to fit on one 72 macrocell device. I have noticed in the schematic method that if you can avoid using comparators and replace with large AND and OR matrixes you really can save macrocells. For example, my timing generation for V and H Syncs are done with a single 8 bit counter, a 4MHz source and large AND with OR gates on inputs. That way I can generate a 4uS pulse within a 64uS time period.
     
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