CPLD Clock Generation

Discussion in 'Embedded Systems and Microcontrollers' started by DrNick, Apr 18, 2009.

  1. DrNick

    Thread Starter Active Member

    Dec 13, 2006
    110
    2
    Hi Everybody,

    I've been playing with a coolrunner II test kit and thought I'd try doing some coding in VHDL. As my first little experiment to get used to VHDL I figured that I should make an LED blink...

    Long story short, I can get the board to turn the LED on and off (not a difficult task), however I am trying to generate a clock that will turn it on and off at 1 Hz. However when I flash the following code, it appears that I always get 50% duty cycle at the same frequency regardless if I tell the clock to have a 100 second period or 1 nano-second period. Any help?

    Code ( (Unknown Language)):
    1. library IEEE;
    2. use IEEE.STD_LOGIC_1164.ALL;
    3. use IEEE.STD_LOGIC_ARITH.ALL;
    4. use IEEE.STD_LOGIC_UNSIGNED.ALL;
    5. ---- Uncomment the following library declaration if instantiating
    6. ---- any Xilinx primitives in this code.
    7. --library UNISIM;
    8. --use UNISIM.VComponents.all;
    9.  
    10. entity blink is
    11.     Port (A : in std_logic; --A not used currently...
    12.             B: out std_logic);
    13. end blink;
    14.  
    15. architecture blinker of blink is
    16.              --set up state machine variables
    17.     type state_type is (st0, st1);
    18.     signal ps, ns : state_type;
    19.     signal ck : std_logic := '0';
    20.    
    21. begin
    22.              --setup clock
    23.     clk : process
    24.     begin
    25.     ck <= not ck after 1000 ms;
    26.     end process clk;
    27.    
    28.              --go to next state on next clock cycle
    29.     sync_proc : process(ns, ck)
    30.     begin
    31.         if (rising_edge(ck)) then
    32.             ps <= ns;
    33.         end if;
    34.     end process sync_proc;
    35.    
    36.              -- machine
    37.     proc : process(ps)
    38.     begin
    39.         case ps is
    40.             when st0 =>
    41.                 ns <= st1;
    42.             when st1 =>
    43.                 ns <= st0;
    44.             when others =>
    45.                 ns <= st0;
    46.         end case;
    47.     end process proc;
    48.    
    49.              --output
    50.     with ps select
    51.         B <= '0' when st0,
    52.                '1' when st1,
    53.                '0' when others;
    54.    
    55. end blinker;
    56.  
    57.  
     
  2. TC Blake

    New Member

    Apr 26, 2008
    2
    0
    You might be absorbing the clocks. Try

    Code ( (Unknown Language)):
    1. ck <= transport not ck after 1000 ms;
    But the real issue here is that you can't separate learning any HDL without also learning how to simulate. I can't stress this enough, because coding is fun but simulation is usually not. (You'll be doing more of the latter than the former - it's how you trace down problems just like yours.) Xilinx usually includes one or more trial simulators with their kits. Otherwise you may want to download the free ISE WebPack from the Xilinx site.
     
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