produce a vhdl code for a clock divider that generates a clock signal of 5KHZ,having one input clock(systems clock) and 1-bit output(the divided clock signal.
2. generate a PWM signal with a frequency of 5khz and 50% duty cycle, produce a vhdl code of a 5-bit counter with one clock input and one 5-bit output.
produce a vhdl code for a 5-bit comparator with a two 5-bit input to be compared and a 1-bit output the result of the comparism
2. generate a PWM signal with a frequency of 5khz and 50% duty cycle, produce a vhdl code of a 5-bit counter with one clock input and one 5-bit output.
produce a vhdl code for a 5-bit comparator with a two 5-bit input to be compared and a 1-bit output the result of the comparism