Hi
I need some help on this assignment i got. We have to use a synchronous counter to enable count from 1 to 6.

Below is the description of the assignment:

I have tried to come up with a schematic for this circuit but unsure if it is correct.

P.S

 

You can follow the link for a free download of a logic simulator - http://www.brothersoft.com/downloads/logic-simulator.html

The LED's are iffy about a direct drive from logic. At the least, you need resistors to control current to a level that won't destroy the IC. You might benefit from looking into debouncing switches.

 

From your interpretation what would you put in the reload logic?

 

It can't work without it. Something has to look for a count of 6 and generate a parallel load with the next clock.

 

so would you need a flip flop or some other gate like a inverter?

 

You might want to try some ideas out using the logic simulator. It only takes a few minutes to set something up.

You might find an AND gate more useful than a flip flop.

 

Ok i have tried the logic simulator and my circuit does not work can you tell me how can i make it count 1 to 6. This is my modified circuit.

 

What are the inputs to that AND gate tied to? It has to use the counter outputs.

 

my mistake i didn't add that when CEP and CET are high the counter will count.

In the CEDAR logic simulator when the led goes light blue what does that mean? And when it goes dark blue what does that mean?

 

Beats me - I use a breadboard or paper.You are still tying the inputs of your AND gate to some unspecified location on the counter.

Think about what pins to use to detect a count of 6. Think about what has to happen after reaching 6 before loading back to 1.

Have you got a '161 data sheet to guide you?
Why are the parallel load inputs attached to a switch? How might they be arranged to let the parallel load enable set the counter to the 1 state?

 

Well, if you connect the parallel load inputs to the inputs on the AND gate would it count 6 times?

Yes i got the data sheet.

 

You can't use inputs as outputs. The parallel load should set the counter state to 1. Think about how to arange the inputs so that will happen.

Think also about the state of the 4 output pins and what they will look like at a count of 6.

 

This is another modified schematic, i pretty sure this is correct, however when i tried to wire it up nothing really happen. Is there anything wrong with my circuit?

 

Why the connections to CEP/CET? All the AND gate needs are the output bits that are true when the count = 6. Check the parallel load setup. You might be loading some value other than 1.

You don't want the counter to go to 1 when the count reaches 6. You want it on the next clock. Add one more AND gate.

 

the clock will pulse when CEP/CET are high

 

the clock will pulse when CEP/CET are high

It's more correct to state that the counter will count if CEP and CET are High, and there is a CLOCK pulse.

 

ok, which connections have i made correct?
Are you saying that i should not connect CEP/CET to the inputs of the NAND gates?

 

You should get the data sheet from Fairchild - [SIZE=-1][/SIZE]http://www.datasheetcatalog.com/datasheets_pdf/7/4/L/S/74LS161.shtml
[SIZE=-1]
It clearly illustrates how the counter functions. Some inputs must be pulled up HIGH (CEP & CET) for proper functioning.
[/SIZE]

 

The circuit below i tested and every time you count it will count from 1 straight to 6 or it will count 1 to 1.

Could you please tell me how to count 1,2,3,4,5,6. I really need to finish it.

 

The second NAND will be low whenever the count is not 6, so the counter will always parallel load on the clock. Your connection to Vcc for D3 sould force the parallel load to produce a count of 8, not 1. CET & CET are floating, and will produce strange results. All unused inputs to logic must be tied HIGH or LOW for proper functioning.

That Fairchild data sheet has the timing diagram to illustrate all counting conditions. You need to use it to see how the IC functions. Every other piece of logic you encounter will have similar constraints to its application.