# counter design

Discussion in 'Computing and Networks' started by arivvu, Dec 28, 2012.

1. ### arivvu Thread Starter New Member

Sep 7, 2012
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i need to design a 4bit counter (start counting from 0 to 15), using 3bit counter (which counts from 0 to 7).....can somebody help me....?

2. ### Brownout Well-Known Member

Jan 10, 2012
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Simply not possible.

3. ### davebee Well-Known Member

Oct 22, 2008
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If you ANDed the three output bits from the counter, and used the result to toggle a flipflop when the three bits are no longer all high, then you could use an output bit from the flipflop to provide the fourth bit.

4. ### THE_RB AAC Fanatic!

Feb 11, 2008
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Isn't it simpler than that? Each next bit is set HI, when the previous bit transitions from HI-LO.

So it only need to detect HI->LO transition of the highest bit in the 3bit counter.

5. ### WBahn Moderator

Mar 31, 2012
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Does the 3-bit counter have a carry out?

Do all four bits need to be synchronous?

Should this be in the Homework Help forum?

6. ### davebee Well-Known Member

Oct 22, 2008
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RB, I don't think so, because the 3rd bit will go high by itself when the 3 bit counter hits the count of 4. You only want to toggle the high bit when the 3 bit counter exits the count of 7, after all three bits have gone high.

7. ### WBahn Moderator

Mar 31, 2012
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If you are using it as a ripple counter, then you can clock the next stage by the falling edge of the msb of the prior counter segment. But if you want the two segments to be synchronous, then you need to detect the terminal state and use it as a count enable signal to the next stage.

Oct 22, 2008
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