i guess you store your pre-last count each time and then compare it to next count output
suppose the count occurs at rising edge _↑¯ of a clock so you store your compare buffer
at falling clock
CLK _/¯\_/¯\_/¯\_/¯\_/¯\_/¯\_/¯\_/¯\_/¯ -- 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 -- clock
CT0 _/¯ ¯\_ _/¯ ¯\_ _/¯ ¯\_ _/¯ ¯\_ _/¯ -- 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 0 1 1 2 2 3 3 4 4 5 5 6 6 0 0 1 -- counter lowermost output
BUF _ _/¯ ¯\_ _/¯ ¯\_ _/¯ ¯\_ _/¯ ¯\_ _ -- 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 0 1 1 2 2 3 3 4 4 5 5 6 6 0 0 -- inter buf (D-trigger)
CPB _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ -- 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 -- compare buffer (D-trigger)
( there is missing control logic for each D-trigger -- which is too easy to figure out)
( here is missing initallizing logic SET/RESET buffers -- it is possible to implement a circular cycle so if compare buffer is to become 0 its set to 7 instead - quite a lot of extra components to counter - but not yet too complex)
which may be not the optimal solution in a sense of component count or the circuit cost and power draw or the Max. speed of operation . . .
ha! , forgot -- you have to implement another counter CT.B to count the CPB times each time the CT0 increments - so the CLK for CT0 has to be "masked" or enabled for CT0 each time CT.B "reaches CPB and is about to reset** that is at next rising CLK" - it's a bit messy to grasp and implement - but if you can simulate or draw the timing diagrams it's all trivial - theres no point anyone else draw such a simple "pure discreet logic" for you - though it can be and fast set up in excel where each next line updates from previous - as each line corresponds to consecutive system states in time - each column is certain output Excel logic can be implemented fast as :
A1 and B1 = C2 =+A1*B1
A1 or B1 = C2 =+0+((A1+B1)>1) -- if you omit starting +0+.. excel displays TRUE or FALSE if you include +0+.. Excel displays 1 or 0
not B1 = C2 =+0+(B1=0)
A1 xor B1 = C2 =+0+(A1<>B1)
e.c.
which is insane but a possibility when there is no alternatives at the time or task is too simple to implement elsewhere
the .zip contains non-cycling v. of CT0 (CT.A) only not CT.B
displays i,j,a values
from what we see is also possible to use only one up down counter that accepts presetting its data by bits as the 74x193 does
and using a lot of registers to shift data in and out , hold the values bing compared (a minor ALU if you like) . . . there are a way too many possibilities to do this
counts from 0 to j
if this is a course excercise then it also might be that what they want to see is counts from 0 to j² or from 1 to j² or who the hell knows because once again we don't have a purpose for this thing represented e.g. what's it gonna be or for what it is for (this place - the Planet Earth - is hopeless . . .)
e.g corrected scripts
v.1
come on ? it <snip> but it will be good to solve this here so years after people searching the web can find their answers - for example lots of UART stuff(useful information) comes from the 1980-s postings and the only valid/practical transformers magnetic chain descriptions come from before WWII scans - so over the 80ya !!!!
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If you want a counter that counts down from 7-squared to 1-squared then recycles, an important question is - what is the output? Do you want the result to appear on a 2-digit display, present as a 6-bit binary number, present as a 7-bit BCD number, or what?