In an effort to study for my upcoming test I've designed a few counter/shift register circuits and I'd love it for somebody to quickly double check my work so I can confirm that they are indeed correct.

The first figure attached is an up down counter using T Flip-Flops.

The second figure attached is and up down counter using JK Flip-Flops. (It's essentially the same as the T Flip-Flop schematic but then inputs J and K are wired together)

Finally the last figure is a universal shift register (entails both left and right shifting capabilities) and parallel load. I realize on this one I may have mad a slight error.

If shift = 00 I should have wired the outputs of each flip flop to 00 bit on the multiplexer running to their input. This way it would have simply held its input while waiting for a shift command.

Does anyone else see any problems with my circuits?

 

Circuits 1 and 2 are correct.
On circuit 3, the register, it is imperative that you connect input 00 of the MUX with the output of each FF.

If not, on the new clock cycle, the D-FF will "see" a hanging D-input pin which transmits an indefined input value.

 

Circuits 1 and 2 are correct.
On circuit 3, the register, it is imperative that you connect input 00 of the MUX with the output of each FF.

If not, on the new clock cycle, the D-FF will "see" a hanging D-input pin which transmits an indefined input value.

Okay thank you for verifying that Georacer.

So all three would be correct if I simply connect the output of each flipflop to the 0 pin on the MUX's?

 

Yes, that's what I said. You need to recycle the information in every clock cycle.

 

Yes, that's what I said. You need to recycle the information in every clock cycle.

Thanks again! Now I know what I'm studying is indeed correct!