Hi,
I'm using 8051 uC

I learned that since ROM is more slow than RAM, then part of the ROM is copied into RAM, to allow faster access for fetching instructions into the Instruction Register.

I have 2 questions please:

1. which part / content of the ROM is copied into RAM?
How can you tell it?

2. The copy of the ROM into RAM is done for fetching instuctions into the Program Counter?

Thank you very much.

 

It's called Vector Remapping. And apparently, you need to have hardware support to do so, which I'm afraid the 8051 uC (and its variants) don't have. (I'm not very sure about this point, maybe somebody else would help clarify this).

Check out 'Vector Remapping' on the ARM reference pages. They have a couple of assembly instructions there.

 

The 8051 architecture has two available memory spaces. Program Space and Data Space. The Program Space is normally read-only and is accessed with the control signal PSEN* (Program Store ENable). This signal is active low and normally connected to the OE* (Output Enable) pin on an external memory. The maximum size of the Program Space is 64 K Bytes. It can be implemented with any combination of internal ROM, external ROM, OR External RAM.

The Data Space is also 64K bytes in size and is accessed with RD* (Read) and WR* (Write). These control signal are only generated by specific instructions that use indirect addressing and the Data Pointer (DPTR) register.

I can imagine a system where a RAM chip could be mapped to both Program Space for instruction fetching, and Data Space for transferring data to the RAM. What I can't get my head around is how you would implement the clock switching to run slow during the copy from ROM to RAM, then change to a higher speed clock/oscillator to run out of fast RAM. If you can do that, then by definition you've given up the advantages of a single chip microcontroller. Internal memory will almost always be your best bet on a cost basis.

 

Hi Papabravo,

Thanks a lot for your great post!

It is very informative and helped me understanding!

Please regard my comments below.

The maximum size of the Program Space is 64 K Bytes. It can be implemented with any combination of internal ROM, external ROM, OR External RAM.

Are you sure that the max. size of the ROM is 64KBytes?
In the 8051 uC of TI, there's 128KB Flash Program Memory (i.e. ROM).

However, I wonder, as this 8051 TI uC has 16-bit address, how can it read from 128KB Program Flash? (2^16 is only 64K).

The Data Space is also 64K bytes in size and is accessed with RD* (Read) and WR* (Write). These control signal are only generated by specific instructions that use indirect addressing and the Data Pointer (DPTR) register.

The Data space of the TI's 8051 is only 8KB SRAM actually.

 

The addressable space is different from the implemented space. As you have observed there is more ROM in your TI variant (128 KB) than can be addressed with a 16-bit address bus. Some additional mechanism is required to select a 64K subset of the 128K available.

For the Data Space, only 8K is implemented but 64K is addressable without adding additional hardware. Just like with the ROM if you add external bank selection harware you can expand the Data Space to anything you want.

You still cannot execute code from Data Space. Data space can ONLY be accessed via MOV @DPTR type instructions.

It is permissible to map a section of memory so that it can be fetched via PSEN*, read via RD*, and written via WR*. That way you could get code execution out of non read only memory.

 

Thank you very much Papabravo