Confused With Circuit State Diagram and PS/NS Table

Discussion in 'Homework Help' started by Mr_K, Mar 9, 2007.

  1. Mr_K

    Thread Starter New Member

    Mar 9, 2007
    2
    0
    Hello, I'm doing some studying for my digital circuits class by looking at previous tests, and I've come across a problem that I cant make sense of.

    The problem is such:

    [​IMG]

    Theres a few things I dont understand about this.

    The first thing is is the PS/NS table. I understand how the y1+ and y2+ outputs were derived from the D Flip Flops, however, the Z output is described as a function of the inputs (Y1 or NOT Y2) which doesnt make sense to me since the inputs get thrown into the Flip-Flops. Shouldnt Z be a function of Y1+ and Y2+?

    Secondly in the state diagram, the only variables that seem to be accounted for are Z and X. I don't understand why the inputs Y1 and Y2 are not represented in the diagram and I can't make sense of it.

    I would really appreciate some help on this, as I've had no luck so far figuring it out myself. :(
     
  2. n9352527

    AAC Fanatic!

    Oct 14, 2005
    1,198
    4
    The real input to the state machine is X only. Y1 and Y2 are the feedback input and are not supplied from outside. This is why only X and Z are accounted for.

    You have to appreciate that at any moment in time, there is respectively only one value for Y1 or Y2. The notations Y1+ or Y2+ are there only to show that those will be the next values of Y1 and Y2 after clocking. Thus changing the state of the machine.
     
  3. Mr_K

    Thread Starter New Member

    Mar 9, 2007
    2
    0
    Thanks, that clarifies things up a bit.
     
  4. ne0codex

    New Member

    Feb 10, 2010
    1
    0
    The state table uses a notation that's different from what my professors have been using, we're instructed to put x=0 and x=1 under the NS, thus creating two columns in the NS and PS.
    I have a question about the state graph though, I see that it is supposed to be State/Z-output, but if that's the case, why isn't there a logic 1 underneath state 11 and 10 since both have output-Z of 1?
     
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