Conceptual difficulty for the realization of a FPGA PWM design

Discussion in 'Embedded Systems and Microcontrollers' started by Obanion, Jan 1, 2010.

  1. Obanion

    Thread Starter New Member

    Nov 26, 2009
    24
    0
    Hi guys,

    I'm working on the creation of a PWM module for MOSFET gate control for an LED, and I'm stumped in terms of operation theory. Essentially, I'm uncertain of the counter values that I require the the impact that it will have on the resolution of my duty cycle.

    I require a switching frequency of 100 KHz, and the FPGA that I'm using has a clock of 50 MHz. I understand that in order to create the PWM signal, I must use a counter to count up and then compare the reference signal to it, and this will allow me to specify the correct duty cycle. I'm working with a duty cycle range ~0.2 to 0.4.

    My PWM reference signal is going to be provided by a feedback network, where the input to the feedback network is going to be a 12 bit ADC. Now this is the part where I'm very unsure of what to make of it.


    I figure since I have a 12 bit resolution, I can have 2^12 = 4096 different distinct values between 1 and 0 (or 10,000 and 0 to make things easier computation-wise). The maximum number that I can count to in the timeframe of 100 KHz is 50MHz/100KHz = 500, much less than 4096. Does this mean that the resolution of my duty cycle is going to be much reduced? Is there even a point of using a 12 bit ADC if I can't count fast enough? It seems kind of ridiculous that I can't update the duty cycle every period because I have to wait for a counter, even though I already have the data.

    Am I totally wrong in my thinking? I just can't seem to get a grasp on this in a conceptual fashion.

    I'd very much appreciate your input. If there's any information that I forgot to include that would make this easier to understand, please let me know.

    Thank you,

    Obanion
     
  2. Dragonblight

    Active Member

    Aug 19, 2009
    35
    0
    Your high ADC issues can be fixed by keeping the levels low. If I know what i'm talking about, then you can use a higher voltage referance and use a significantly smaller portion of that ADC register.

    Question: What uController are you using? If it comes with a built-in PWM your job just got easy.
     
  3. JotDot

    New Member

    Jan 1, 2010
    3
    0
    You wanted input? You asked for it. Here goes:

    Let's look at what you have:

    1) 4096 is approx (1/4096)*100 or 0.0244 of a percent. Do you really need that kind of accuracy over the entire input range?

    2) At 100kHz, this is a pulse width of 10uS. Chopped up into 4096 pieces, this implies a 2.44 nS accuracy. Is that really needed? You'd probably have more issues with board layout, - simply getting a clean undistorted signal out. This does imply an almost 500MHz clock!

    3) How long does it take the ADC to convert relative to the slew rate of the input signal? ie: it is no use being accurate to 0.0244 percent when, by the time the ADC has that value, the input has changed by a few percent. (This problem depends on the type of application). My main point is that the instantaneous output will lag the input (due to conversion delays) and can be off quite a bit (percentage) if the input changes too fast. This may be a design factor.

    Back to your design attempt: Yes, at 50MHz as you stated, the most the counter would get to is 500 for a 10uS pulse. This means a 9bit ADC would suffice (or just use the most significant 9 bits of the 14 bit ADC). This would give you (1/512)*100 or about 0.2% accuracy over the ADC input range.

    Another way of looking at it: 50MHz clock gives you 20ns "blocks" that will make up your 10uS PWM signal. If 20nS is too wide, then a 50MHz clock is too slow. If 20nS granularity is more than fine for your 10uS pulse, then the issue is the ADC gives more precision than needed.

    If you need more accuracy then knowing your fpga is vital. If I remember correctly, the Altera cyclone series have a PLL in it so you can lock on to the 50MHz and effectively increase the clock rate - but the details I'm unsure of. Other fpgas might be able to do the same. But again, at those rates you have to watch the design. Propagation delays could affect accuracy when dealing with narrow windows like 2nS.

    Have fun. Hope I helped and was not too far off what you asked for.
     
  4. Obanion

    Thread Starter New Member

    Nov 26, 2009
    24
    0
    Thanks for the input guys. Your help was very useful. I think that accuracy is required due to a few simulations that I've performed using SPICE models. Ideally, I'd like to keep the current through the LEDs at 700 mA +/- 2 %. I figured that the 12 bit ADC would allow for a lot of headroom, and allow a good amount of duty cycle variation. In my SPICE models, at 30 V input, a slight change of duty cycle has big changes in the LED current. For instance:

    At 30 V


    Duty cycle = 0.33848 --> LED current = 700 mA +/- 1%

    After trimming a few bits off:

    Duty cycle = 0.338 --> LED current = 0.680 mA +/- 1%
    Duty cyce = 0.340 --> LED current = 0.750 mA +/- 1%

    Now, even with a slight increase in duty cycle to:

    Duty cycle = 0.342 --> LED current = 0.820 mA


    I'm worried that a low accuracy is going to blow the LEDs up and have a large brightness variation, so that's why I'd really like to keep it with a tight accuracy. I think I'll have to work something out. I can't change the operation frequency now since I have most of the components, so that's a no-go.

    The PLL sounds interesting, but I'm nearly positive I won't be able to get that 500 MHz mark, and if I did, I agree that I'd have problems to worry about :p

    I'll have to think about this for a bit. I guess the only real way to see what will happen is to just plug everything in and test it, but that won't be for a while until I can get the feedback and the ADC interface implemented.

    Anyway, thanks a lot for your help. It really shed some light on the issues that I was uncertain of.
     
  5. Markd77

    Senior Member

    Sep 7, 2009
    2,803
    594
    A capacitor in parallel with the LED would make the voltage more stable which should help with constant current. You might find a small oscillation around the desired current. It will slow the response down if you are using it for data transmission so might not be ideal in that case. Try putting a few different values in in SPICE and see if it helps.
     
  6. Obanion

    Thread Starter New Member

    Nov 26, 2009
    24
    0
    I think I'm okay in that respect. I have a large 470 uF output cap for the LED to lower the ripple. Thanks for the input.
     
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