I want to ask a question about common source circuit with inductive load.
For example, there is a circuit as in the picture. I removed coupling capacitor and arrange it as below to make it simple, though I know it is only in theory not practical.

VGS: Bias voltage to make M operate in saturation region.
vgs: Small signal voltage that need to be amplified.
Let's assume that VGS= constant so that the transistor is in saturation region.
And the small signal:

\(v_{gs} = V_{0} sin( \omega t)\)

The transconductance of the transistor, gm, is:

\(g_{m} = \mu _{n} c_{ox} \frac{W}{L}( V_{GS} - V_{TH} ) = constant \)

Drain current, iD:

\(i_{D}= g_{m} v_{gs}= g_{m} V_{0}sin( \omega t)\)

The voltage across the inductor:

\(v_{L} = L \frac{d i_{L} }{dt} = L \frac{d}{dt} (g_{m} V_{0}sin( \omega t)) = \omega Lg_{m} V_{0}cos( \omega t)\)

The voltage at D:

\( v_{D}= -v_{L} + V_{DD} = - \omega Lg_{m} V_{0}cos( \omega t) + V_{DD}\)

If gm, ω, VGS are fixed, then the magnitude of vL is directly proportional with L. We can make it lager arbitrarily by choosing the value of L.
And therefore, the voltage swing at D can be very large beyond the range from 0 to 2VDD, right?

I have heard somewhere that the maximum voltage swing at D is 2VDD and ranges from 0 to 2VDD.
Is that right?

 

If you make the DC analysis of the circuit, the voltage at D at operating point is VDD (L behaves as shortcut).

Meaning that, if ever oscillations are possible, these will be done from this operating voltage VDD. Assuming that the MOSFET can swing from one extreme to the other, the output voltage will be from 0 to 2*VDD (ac oscillation of VDD volts amplitude).

 

The voltage across the inductor:

\(v_{L} = L \frac{d i_{L} }{dt} = L \frac{d}{dt} (g_{m} V_{0}sin( \omega t)) = \omega Lg_{m} V_{0}cos( \omega t)\)

Are you sure of the sign of this formula? shouldn't the relationship between VL and IL be negative.

 

If you make the DC analysis of the circuit, the voltage at D at operating point is VDD (L behaves as shortcut).

Meaning that, if ever oscillations are possible, these will be done from this operating voltage VDD. Assuming that the MOSFET can swing from one extreme to the other, the output voltage will be from 0 to 2*VDD (ac oscillation of VDD volts amplitude).

In DC mode, VD(dc) = VDD
In AC mode, VD(ac)= -gm*(ωL)*vgs
=> The voltage at drain of the transistor:
VD = VD(dc) + VD(ac)= VDD - gm*(ωL)*vgs
For example, vgs = Vo*sin(ωt).
VD = VDD - gm*(ωL)*Vo*sin(ωt)
Huh, a bit different with the one I made above. Maybe, I mistake somewhere.

My confusion is why you know that 0 < gm*(ωL)*Vo < VDD ?

 

I have seen the term "open channel condition". Please help me with the question.

 

I also never heard about "open channel condition".
But I suspect that Id_max = Vdd/Rd = open channel condition.

 

Thanks Jony. That seems right. However, I wonder why the characteristic Vgs-Ids depends on its load, Rd.
And can you explain about maximum voltage swing at D is 2VDD?

 

Here is the part talking about open channel condition in my book.
http://www.weenysoft.com/online/p3r68-cdx67/prpha-7rro8.pdf

 

And can you explain about maximum voltage swing at D is 2VDD?

For the inductive load, the DC voltage at drain is equal to Vdd. And so the maximum negative voltage swing is from VDD to 0V.
And so in order to keep the waveform symmetrical we "limit" the positive voltage swing to 2VDD (swing from Vdd to 2Vdd).

 

For the inductive load, the DC voltage at drain is equal to Vdd. And so the maximum negative voltage swing is from VDD to 0V.
And so in order to keep the waveform symmetrical we "limit" the positive voltage swing to 2VDD (swing from Vdd to 2Vdd).

In other cases, for example, in AB or C class power amplifiers, there is a filter at output. And therefore, we don't need to keep the voltage at drain symmetrical.

Is that right?

Can you help me derive that formula below in the part of my book above?

\(P_{OUT} = \frac{ V_{DD}^{2} }{2 R_{OPT} } \)

 

In other cases, for example, in AB or C class power amplifiers, there is a filter at output. And therefore, we don't need to keep the voltage at drain symmetrical.

Is that right?

I don't know

Can you help me derive that formula below in the part of my book above?

\(P_{OUT} = \frac{ V_{DD}^{2} }{2 R_{OPT} } \)

the average power is equal to

P = Vrms * Irms = Vrms^2/R

But if we use Vpeak instead of Vrms we have this situation

P = Vrms^2/R = [ (Vp/√2)*(Vp/√2) ]/R = (Vp²/2)/R = Vp²/2R

 

Well, I got stuck at that for two days. I know the formula but didn't think about it.

Please help me with this part.

This value is called optimum because it is the load that provides the best
linearity to the PA. This is because the drain current and voltage simultaneously
swing to their maximum linear capacity, as shown in the idealized VDS–IDS model
in Fig. 3.3. It can be observed that the drain current has reached its maximum
linear swing, from 0 to IMAX, and at the same time the drain voltage value, thanks to ROPT, swings from VDD to 2VDD, which is also its maximum linear swing.

I don't know why this optimum resistance provides the best linearity to the PA. To me it provides maximum voltage swing not linearity.
And in the figure drain current and drain voltage not reach their maximum values at the same time. As VDS max IDS = 0 and vice versa. Can you tell me what the book meant here?

 

It seems that they assume that ID_max = IDmax for a given MOSFET and use idealized VDS–IDS model. So in this case Ropt provides in the same time the best linearity and max power at load.

 

For MOSFET, the power dissipation in transistor:
P = Vds*Ids and we always want this as low as possible, right?

 

For MOSFET, the power dissipation in transistor:
P = Vds*Ids

Yes

and we always want this as low as possible, right?

Yes, but in some circuit we have to deal with it. For example in class A amp
P = Id_Q * Vds_Q
Q = quiescent point

And this power dissipation is independent of a active device we choose to use in the amplifier.

 

Thanks Jony. Now I understand it better. I will read about them again and ask later.