# Combining 2 Clock Signals-Need help with logic circuit

Discussion in 'The Projects Forum' started by KP2008, Aug 7, 2011.

1. ### KP2008 Thread Starter New Member

Aug 7, 2011
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Hello All. I am scratching my head trying to figure out how to accomplish what (at first) seemed like a simple task. In the diagram below, I have two signals (CLKA and CLKB) that vary in frequency (from 5Hz to 20KHz) but always have the same phase with respect to one another. I am trying to accomplish the waveform labeled "IDEAL OUTPUT" the simplist way possible. More info:
• The yellow box shows one complete cycle which repeats over and over. In this cycle, there are 64 positive edges on CLKA and 2 on CLK B.
• I desire an output that has has 16 positive edges (width of pulses not important) with the third pulse removed (IDEAL OUTPUT).
• If removing the thrid pulse is too complicated, removing the pulse directly after the CLKB reference pulse would suffice (ALTERNATE OUTPUT).
• It does not matter if CLKB grabs position 0 or 32 as the postive-going transition upon startup. If this happens, signal CLKB/2 would be inverted, and missing pulses will occur on output pulse 11 insetead of 3(IDEAL)...or output pulse 9 instead of 0 (ALTERNATE). This is ok as long as there is only one missing pulse in the complete output cycle of 16 pulses.
I hope that made some sort of sense! I'm a newbie, so please be gentile. Any suggestions or help would be SO GREATLY APPRECIATED!

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2. ### Kermit2 AAC Fanatic!

Feb 5, 2010
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To get the alternate timing signal

Divide clkA by 4

Use clkB to inhibit the output of the divide by 4, to remove a pulse at that point.

Use clock B/2 to activate the inhibit output of clkB, so the missing pulse is only present when clkB/2 is positive.

3. ### SgtWookie Expert

Jul 17, 2007
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I've attached a schematic and simulation of one way to get your "alternate output" using four D-type F/F's and a quad NAND gate; basically what Kermit2 was saying.

To get your 1st output, a counter would need to be added.

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4. ### praondevou AAC Fanatic!

Jul 9, 2011
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Sorry about the small oscillograph, no idea how to make it bigger. Gives you the ideal output.Add a divider for CLKA (by 4).

edit: oops, cross-posting
edit2: the second picture is better. the circuit stays the same.

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• ###### zoom output.PNG
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5. ### SgtWookie Expert

Jul 17, 2007
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That'll do it.

Here's a version of the same thing in TTL; I just swapped in/out a few gates and changed the plumbing.

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6. ### praondevou AAC Fanatic!

Jul 9, 2011
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Wookie, if I understood right he wants to remove the 3rd pulse from CLKA/4 not the 3rd from CLKA. Also, the CLKA/4 doesn't look like CLKA/4 in your last post.

Please have a look at my last post. The only thing I didn't do was dividing CLKA by 4.

Last edited: Aug 7, 2011
7. ### KP2008 Thread Starter New Member

Aug 7, 2011
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WOW WOW WOW and THANKS GUYS!!!
I really appreciate the time you took to create such great schematics and waveform outputs!!!!! So incredibly helpful!
The only question I have left before I start soldering is how to make sure the circuit initializes corrrectly when it starts up. I probably should have mentioned this before, but when powered up, the clocks might hit the inputs of this logic circuit starting at any position (0-63) on my diagram. How can I assure that the output pulses happen on 0, 4, (8), 12...etc, instead of like 1, 5, (9), 13...etc if the logic is powered up right before pulse number 1.
I guess my question is....how would I implement a mechanism where The rising EDGE of CLKB/2 makes sure the CLKB/4 counter resets to 0? before the next rising edge of CLKA? (to prevent the output from being shifted from 1-3 pulses). Do I need to worry about this?
Thanks again x a million. This forum is awesome!

8. ### SgtWookie Expert

Jul 17, 2007
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What I read on his plot was "Remove 3rd pulse (from clka/4) after CLKB/2 goes high".
But, maybe I'm wrong.

Yes, I forgot to change the label; obviously it's not CLKA/4 anymore; I basically just took the previous schematic I had and pushed things around, and forgot to fix some labels.
[eta]
I've attached a schematic/timing diagram that reflects the updates.

I don't know if they need that or not; if they do it'll take some more D-type F/F's.

[eta]
Meanwhile, as our OP mentioned, neither of us have an initialization sequence shown.

• ###### KP2008 clock divider 2.png
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9. ### praondevou AAC Fanatic!

Jul 9, 2011
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No you are not wrong, but it's the 3rd pulse of CLKA4, the way you did it in your first post. Your 1st post looks exactly like his diagram, your last doesn't.

10. ### SgtWookie Expert

Jul 17, 2007
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dOH! (in my best Homer Simpson voice) well, I stepped in THAT one.

I guess I don't see where you're getting your CLKA/4 in your schematic.

11. ### praondevou AAC Fanatic!

Jul 9, 2011
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You don't see it because I didn't draw it. The CLKA/4 he has yet to add.

I may be mistaken, but I still think that your two post are different (apart from the alternative / ideal output thing). In your first you remove the 3rd pulse of CLKA/4, in your last you remove it from CLKA.

Just trying to understand here. Am I right or should I get some coffee?

12. ### SgtWookie Expert

Jul 17, 2007
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You know, despite the evidence I've presented thus far, I'm really not retarded.

I just about had it figured out in the 1st post, and then boy I really goofed it.

13. ### SgtWookie Expert

Jul 17, 2007
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OK, here's go-around #3; it looks right to me, but I'm tired.

Care to have a look?

The start-up reset is going to have to be another day, as I'm about worthless at this point.

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14. ### praondevou AAC Fanatic!

Jul 9, 2011
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Well, that looks exactly like what he wanted. I was trying to figure out how to divide the CLKA and to get the same pulse width, kind of obvious once I saw the solution...

15. ### SgtWookie Expert

Jul 17, 2007
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Well, darn - I found a problem.
I had CLKB starting at the same time as CLKA - but that's not how it works; CLKB's rising edge is when CLKA's is falling. When I corrected the waveform generator for CLKB so that it wasn't delayed, it threw the timing off for everything... so I swapped out the NAND gates and swapped in a hex Schmitt-trigger inverter so that I could delay the rising edge of CLKB just a tad, which makes the timing work again.

See the attached. the "b" plot is clkb, bslo is the clkb with the slow RC rise time that's been squared up by the Schmitt trigger.

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16. ### SgtWookie Expert

Jul 17, 2007
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KP2008, I guess you think we forgot all about you, but it was important that we get the basic logic & timing correct before we got to the reset portion.

It seems that the reset needs to occur on the rising edge of Clock B, as that's where the baseline is; timing begins with Clock B. However, the missing pulse is after every other ClkB - does it matter which ClkB pulse it resets on? There doesn't seem to be a way to tell.

17. ### KP2008 Thread Starter New Member

Aug 7, 2011
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First of all......I have to give THE BIGGEST THANKS to all of you who have really thought about this brain-bender of a challenge!!!! I have never experienced a forum where people are so willing to help!

To answer your question....no, it does not matter which ClkB pulse it resets on.....as long as the next one is "ignored". My original description (and diagram) of this portion may have been confusing but let me describe it in a way that might be a bit clearer:
• With the two clock inputs (ClkA & ClkB), as shown on my original diagram, I need a circuit to combine the two clock signals into a single clock signal.
• The first positive-going event of ClkB will be considered "Pre-Position 0" and the following positive edge will be considered "Pre-position 32". It does not matter if the CLKB/2 signal is inverted and the missing pulse occurs on the 12th output pulse instead of the 3rd (in my diagram). Idealy, the output clock would stay at Logic-0 until the first ClkB positive edge is received...the counting will start, and the next ClkB pulse will be ignored (not create a missing pulse).
• The purpose of ClkB is to allign the phase of the ClkB/4 and to determine the position of the missing pulse.
• When the circuit powers up....the first positive ClkB edge will create ClkB/2 to go high....and the very next ClkA positive edge should create the first positive edge of the output (Position 0 in diagram). Depending on when the circuit starts, it may actually be at Position 32, but that's fine. You are correct in the fact that there is no way to tell the difference if you wanted to.
• The missing pulse should occur on the 3rd output pulse after a ClkB EDGE (and ignore the next ClkB pulse).
I hope this description helps clarify things and I can't thank you all enough!

It might also help to describe where this signal comes from, and what I am trying to accomplish. The two clock singals come from two Variable Reluctance sensors on a spinning flywheel for a 4-cylinder 4-stroke sprint car engine. The VR snesors signals go into zero-crossing detector circuits which creates 0-5 logic signals at points where the sensors line up with the metal teeth. ClkA comes from a sensor on the 64 starter gear teeth, and ClkB comes from two pins mounted 180degrees apart on the backside of the flywheel. This is a pretty antique (but awesome) engine with a WHACY ignition triggering scheme that I am trying to adapt a modern afermarket ignition system to. These modern ignitions use a "missing tooth detector" to determine the angular postion of the flywheel...and to determine when the spark should occur (counts teeth + time to determine when to fire). The ignition I want to use needs a 16 pulse per revolution signal with one missing pulse (ideally at 150deg BTDC...which is my IDEAL output in diagram). The engine has two coils and two distributors (2 cyl each) and will fire CoilA at positions 0 and 32....and CoilB at postions 16 and 48 (plus or minus advance). The reason it does not matter if CLKB/2 gest inverted is that the engine will not care if "Cylinder 1" or "Cylinder 3" corresponds to postion 0 on my diagram.....because the distributor will always tell Coil A where the spark goes.

I hope I didn't overly confuse everyone AND THANKS AGAIN!

-KP2008

18. ### SgtWookie Expert

Jul 17, 2007
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Well, here's the reset until a good clkb is received.

[eta]
The rising edge of clkb on the far left of the plot isn't "seen" by the rest of the circuit, as I've selected SPICE options that cause the power to the circuit to be delayed (too brief to be seen at this plot scale), and the rising edge of clkb occurs at time zero.

I had to add D-type f/f U6 to take care of providing a CLR signal. When CLR is low, all of the f/f's except for U5b are cleared; U5b is constantly being cleared after every clka so it doesn't need to be cleared by CLR.

The CLR signal is also used to enable the output via AND gate U4c; no signal gets out until U6b has seen a rising edge from clkb.

R2/D2/C2 cause U6b to be cleared on power-up; the CLR input is held low briefly due to the RC time constant. D2 provides a quick discharge path for C2 when power is removed; otherwise on next power-up the state of U6b could not be guaranteed. When the f/f is powered up and the CLR input is low, the Q output goes low and the Q\ output goes high. The Q output going low causes the other f/f's (with the exception of U5b) to also be cleared.

I'm not really comfortable with using an RC time delay on clkb. It works in this simulation, but it may not work at higher frequencies.

• ###### KP2008 clock divider 3.png
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19. ### KP2008 Thread Starter New Member

Aug 7, 2011
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SgtWookie---I just spent about a 1/2 hour studying and wrapping my newbie briain around your circuit and simulation, and have to say that it is brilliant! It looks like it is able to handle all criteria and behave properly under all circumstances & frequencies.

Thank you so much and this has been such a great learning experience. I can't wait to build it this evening and give it a try! I just picked up a nifty 8-ch USB logic analyzer so I will post a picture of the actual real-world signals once I capture them.

20. ### SgtWookie Expert

Jul 17, 2007
22,182
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It wasn't just me; it really was a group effort. Kermit2 spelled out the basic logic, and I just threw the alternate output circuit together in TTL for fun. Then praondevou came up with a way to obtain your ideal output using a few parts a bit differently than I did, then he was a big help in keeping me honest (it's too easy to overlook things when you are "overly familiar" with a problem). All of the ideas had to be merged together and de-bugged before it went anywhere.

You must use 0.1uF/100nF ceramic or poly metal film bypass capacitors on every IC used in this circuit, or you will have problems. Keep your jumper wires as short as possible. I didn't optimize what pins or ICs I was using to get the most efficient layout; just to get the logic working.

Try it with a 100Hz clkb input, 3.2kHz clka input, and see how the output looks. bslow should have its' leading edge lagging clkb by roughly 55uS-60uS. If it is not in that range, adjust R1's resistance until it is. If there is no delay on the leading edge but delay on the falling edge, check to make sure you have D1 installed correctly. The trailing edge will lag by perhaps 1uS-5uS; not much more though.

This entire circuit could be replaced by a single 6-pin \$0.50 microcontroller operating at 20MHz or higher, and a few lines of programming.