Hi,
this code has no connection between input and output. can anyone please help me to separate the RAM and take data from RAM to do the computation,
The input data should fill the RAM ,
I mean the module RLD should have an input data line which actually fill the Ram location and the circuit is taking data from RAM and do the computation. How can modify the code like that?

 

I'm posting it enclosed in code tags so somebody can be of more assistance:

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL; 
entity RLD is
 Port ( clk : in STD_LOGIC;
 cout : out STD_LOGIC; 
lastut : out STD_LOGIC_VECTOR(7 downto 0));
 end RLD; 
architecture Behavioral of RLD is type RAM_t is array (0 to 15) of std_logic_vector (7 downto 0); 
signal RAM : RAM_t := ( x"AA", x"00", x"FF", x"FF", x"01", x"00", x"00", x"01", x"AA", x"AA", x"00", x"FF", 
x"FF", x"03", others=>x"00"); 
signal idx : integer range RAM_t'range := 0; 
signal rpt : integer range 0 to 255; -- repeat counter max. 255 
signal last : std_logic_vector(7 downto 0) := x"FF"; -- for lastuble-byte check: beware the first byte in RAM being xff! 
signal gl : std_logic := '0'; -- get length out of RAM 
signal phase : std_logic := '0'; 
begin 
process begin 
wait until rising_edge(clk); 
phase <= not phase;
 if (phase='0') then
 if (rpt>0) then  -- something to repeat? 
rpt <= rpt-1; 
else idx <= idx+1;  -- beware of reaching the end of the RAM! 
if (last=RAM(idx)) then  -- next: get length
 gl <= '1'; 
else
 last <= RAM(idx); 
end if; 
end if; 
else if (gl='1') then -- get length
 rpt <= to_integer(unsigned(RAM(idx)));
 idx <= idx+1; -- beware of reaching the end of the RAM!
 end if; 
gl <= '0'; 
end if; 
end process; 
lastut <= last; 
cout <= phase; 
end Behavioral;