CMOS transistor sizing

Discussion in 'Homework Help' started by nyasha, Dec 12, 2011.

  1. nyasha

    Thread Starter Active Member

    Mar 23, 2009
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    Question

    The question is Specify the W/L ratios for all transistors in terms of the ratios of n and p of the basic inverter, such that the worst case tphl and tplh of the CMOS gate are equal to the basic inverter.

    My query

    Okay guys, l am confused on coming up with the size for the transistor C and D in the PDN. Since l already said transistor B in the PDN has a size of 2n, does that mean automatically C and D which are in parallel with B also become 2n ?


    Attempt to solution

    See the attached PDF.
     
  2. Georacer

    Moderator

    Nov 25, 2009
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    No, I think the worst case for the PDN is when the conductive path is trough A-C-D, because this is the longer one. That is why you need a ration of 3n in all of those three.
     
  3. jegues

    Well-Known Member

    Sep 13, 2010
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    The worst case scenario is that which draws the lowest current.

    You have correctly identified this for the PDN and assigned the correct values for QNA and QNB.

    Now consider the case when QNA, QNC and QND are on.

    QNA is already fixed at 2n, so what must you select for QNC and QND?

    It's obvious that the result from the series combination of QNC and QND must be 2n, such that it combines in series with the 2n from QNA giving a equivalent n.

    So what should the values of QNC and QND be such that their series combination produces 2n?
     
  4. Georacer

    Moderator

    Nov 25, 2009
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    @jegues

    Is there any specific reason to start by examining QNA and QCB first, and specifying QCA as 2n, instead of examining QNA, QNC and QND?

    Both solutions are valid, aren't they?
     
  5. jegues

    Well-Known Member

    Sep 13, 2010
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    This is because we are emphasizing worst case design.

    We identify and satisfy the worst case scenario first.
     
  6. Georacer

    Moderator

    Nov 25, 2009
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    But isn't the worst case QNA, QNC and QND? Why do you size QNA as 2n and don't spread the extra size evenly among QNA, QNC and QND?
     
  7. jegues

    Well-Known Member

    Sep 13, 2010
    735
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    The worst case for the (W/L) ratios which is what we are designing for is that which draws the lowest current.

    Surely the supply current will be much less with only 2 transistors operating.
     
  8. nyasha

    Thread Starter Active Member

    Mar 23, 2009
    90
    1

    I emailed my prof with the same question and he said there are many solutions since this is a design question. But the solution he offered me is the same as the one you proposed.
     
  9. Georacer

    Moderator

    Nov 25, 2009
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    I 'll look more into it, but I think that it's worse having a string of 4 gates in series (AND) than having 4 in parallel (OR) and only one of them conducting.

    The reason behind it being that you have 4 times the time delay of the ON and OFF times in the first case.
     
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