CMOS Output: Source v Sink

Discussion in 'General Electronics Chat' started by richard3194, Jan 25, 2014.

  1. richard3194

    Thread Starter Member

    Oct 18, 2011
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    Is the following typical of CMOS output when the output pin is meant to drive a load (directly or indirectly) such as a LED or relay? :-

    * Normally the pin is a source or in a Hi state? (That is, the load returns to a sink.)

    * The source current maximum is typically equal to the sink current maximum.

    Thanks.
     
  2. ronv

    AAC Fanatic!

    Nov 12, 2008
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    Usually they are about the same. Check each data sheet.
     
  3. richard3194

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    Oct 18, 2011
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    Does it make sense to make sink current max greater than source current max?
     
  4. MrChips

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    Make sense to whom?
    Are you the chip designer or the chip user?
     
  5. richard3194

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    Oct 18, 2011
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    Given that when a load is returned to source you have the chance to use your own separate / independent power supply, it seems to make sense that a manufacturer would make sink, or logical low the state of an output pin - for a load condition of "On", as well as providing a higher maximum current when sinking than sourcing.

    But given that you can have added circuitry after the output pin, perhaps there is no particular advantage to a better sink current than source.

    I think you would always tend to use a separate driver transistor after the output pin with CMOS anyhow.
     
  6. MrChips

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    So what's the question?
     
  7. bertus

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    Apr 5, 2008
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    Hello,

    Have a look at page 4 of the attached PDF for the sink and source currents at the different powersupply voltages for the HEF cmos series.

    Bertus
     
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  8. richard3194

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    Oct 18, 2011
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    When they were designing the status of output pins meant to drive loads, did they ever consider making pin status Low the condition for the load being "On"? Or, was it a non issue?
     
  9. crutschow

    Expert

    Mar 14, 2008
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    CMOS digital circuits mostly drive other digital circuits so, for that, you want to make the source and sink current capability equal so that the signal rise and fall times from driving the various external stray capacitances are similar. Gates specialized for driving larger external loads may or may not have equal source and sink capabilities, depending on what they are intended to drive.
     
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  10. richard3194

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    Oct 18, 2011
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    I've been looking at decoder HOLTEK HL12D, where the outputs (D8-D11) usually drive loads.

    Seems that output pins have to be Hi for an On condition of the load.

    I suspect that the industry never specified any particular pin status (Lo or Hi) as a default On condition for loads.
     
  11. bertus

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    Hello,

    Did you read page 5 of the datasheet?
    There is stated that the data output will be latched when 3 times same data is recieved.

    Bertus
     
  12. SgtWookie

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    Jul 17, 2007
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    CMOS 555 timers are usually specified with a 10mA max source, and 100mA max sink capability. Not certain how this came about, but the design is rather "long in the tooth" - even though it hasn't lost much in the way of popularity over the years.

    One basic item favors sinking over sourcing; it's easier to move electrons than holes. This favors N-channel MOSFETs over P-channel, as the gates have to be about 2.5 times larger to achieve the same Rds(on) as an otherwise comparable N-channel device. That means it'll take 2.5 times as long to charge or discharge the gate.
     
  13. richard3194

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    Oct 18, 2011
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    I was trying to teach a friend some electronics, but I was doing some speculating. I drew a CMOS IC with an output pin driving a load. I says, if this pin is source to make load condition "On" it can supply 5V. But if it's sink you can have a variety of voltage powering the load. So, I says, this makes one think it's sensible to have the pin sink current for the "On" condition of the load. But, I also speculated that despite this sort of reasoning, the industry probably never issued a statement that by default an output pin driving a load should be or preferred, sink, or Lo.
     
    Last edited: Jan 25, 2014
  14. ian field

    Distinguished Member

    Oct 27, 2012
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    It did with TTL because of the way gate inputs were designed, when driving the next CMOS gate its literally the gates of a complementary pair of MOSFETs, apart from charging and discharging the gate capacitance - there's virtually no current draw to maintain a given logic state.
     
  15. kubeek

    AAC Fanatic!

    Sep 20, 2005
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    First of all, it depens on what load you are talking about. For example gates of mosfets need both sink and source capability on the outputs to work properly.
    Second thing is that you should never have larger voltage on the inputs than Vcc of the driving ic.

    With open collector/open drain configurations it may be possible to design in higher max voltage than Vcc, but this is rather rare.
    I don´t see any reason for the industry to specify this.
     
  16. richard3194

    Thread Starter Member

    Oct 18, 2011
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    Of course with a CMOS device you might expect logic level Hi on a pin to be 5V (say)

    Yes, there is no advantage. If both mosfets controlling the output pin were identical rating that is rated at 5V and say 3mA (hypothetically) then you could not take advantage of a higher external supply voltage.


    To pass 0.03 mA you need a load of 166R at 5V.

    If the output was to be Hi for load "On" the maximum load wattage would be (0.03 mA x 0.03 mA) x 5V= 0.1494 watts.

    To pass 0.03 mA at 50V you need a load of 1666R

    If you used a 50V external supply, (using the pin as a sink, that is Lo) the load wattage would be (0.03 mA x 0.03 mA) x 1666R= 1.499 Watts.

    That looks like it's advantageous to specify a pin be Lo for the load being in the "On" state, rather than pin set to Hi.

    But, given the mosfet sink rating of 5V, your maximum external supply voltage can only be 5V.
     
    Last edited: Jan 27, 2014
  17. richard3194

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    Oct 18, 2011
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    I don't know if this means anything, but all except 1 example of driving loads (from CMOS) the pin is Hi for the load condition of "On" (Page 586 of Art of Electronics).

    Examples E,G,I,K,L are CMOS sourcing current.

    Is J an example of the exception that proves the rule then?
     
    Last edited: Jan 27, 2014
  18. richard3194

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    Oct 18, 2011
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    Well, in my studies, I'm left with the impression that although not an industry standard, CMOS outputs driving loads will, by and large, source current, when loads are in the "On" state. I've not heard anyone say this is not the case.
     
  19. ronv

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    From what I've seen they almost always source and sink the same current, but you can Google it or read lots of data sheets.
     
  20. richard3194

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    Oct 18, 2011
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    And I'd say: A CMOS output, meant to drive a load like a LED, or relay, will, more often than not, source rather than sink the load - or source an external driver transistor's input. It appears. Which I'm extracting from page 586 of A of E.
     
    Last edited: Jan 29, 2014
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