CMOS OR gate

WBahn

Joined Mar 31, 2012
29,979
It consfuses me that the output is extracted from the drains two transistors.If the transistor Q5 is on it will have current in the drain.And if only Q6 is on we dont have current in the drain?The output is not high because we don't have a path from the gate to a driving source (an input or a supply) that goes through gates that are ON(in the case i mentioned Q6),when Q5 is OFF?
Okay, I think have a glimmer of what is causing your confusion. You seem to be focused on how current flows and that is not a terribly good way to think of it. Instead, think of the transistors in a CMOS circuit as voltage-controlled switches, such as a relay, perhaps.

So consider the two cases below:



Would you agree that the voltage on the output of 'A' is going to be 0V (or LO) while the voltage on the output of 'B' is going to be Vcc (or HI)? Notice that it doesn't matter that no current can flow in either case. If you were to connect a load up the output, then current could flow, but the voltage at the output would remain 0V or Vcc, respectively, thus maintaining the logic level.

(Note that I should have used "Vdd" for the name of my supply. Oh well.)

Now take the next step and replace the switches with voltage-controlled resistors (which is actually a very good model for most CMOS circuits):



When the input is HI, Rn is "ON", meaning that it has a fairly low resistance and Rp is "OFF", meaning that it has a very high resistance. If it would help to have some roughly representative numbers, use 1kΩ for the low resistance and 1MΩ for the high resistance. You thus have a voltage divider that, will result in a very low voltage at the output. When the input is LO, the resistances are reversed and Rn has a high resistance while Rp has a low resistance; the result is again a voltage divider but now it will result in a voltage output that is very close to Vcc.

Either the voltage-controlled switch or voltage-controlled resistor model will work nicely for the vast majority of logic analysis involving CMOS logic. When the gate votlage is HI, an NFET is either a switch that is closed or a resistor that is small, while a PFET is either a closed switch or a small resistor when the gate voltage is LO.
 

Attachments

Top