Hi,could someone confirm someone could confirm whether my analysis of this circuit that implements an or gate with cmos is correct?

I find it a little confusing that the output is extracted from that point.

For the output to be equal to 1(high state) Q5 will always have to be on,right?

I mean is not possible the output to be 1 if Q5 is off and Q6 is on rigth?

Input A Input B
0 0

Q1 ON,Q2 OFF,Q3 OFF,Q4 OFF,Q5 OFF ,Q6 ON

Output = 0

Input A Input B
0 1

Q1 ON,Q2 ON,Q3 OFF,Q4 ON,Q5 ON ,Q6 ON


Output = 1

Input A Input B
1 0

Q1 OFF,Q2 OFF,Q3 OFF,Q4 ON,Q5 OFF ,Q6 OFF

Output = 0 (this is not correct ,since this is a or gate.The state of Q5 will determine wheater the ouput is 1 or 0.Q5 depends on the state of Q2 and Q3.So if Q2 is off and Q3 is ON this means that Q5 will be on?It is not necessary that Q2 is ON in order to Q5 be on to?


Input A Input B
1 0

Output = 0 -->same situation as for the previous situation


Q1 OFF,Q2 OFF,Q3 O3 ON,Q4 ON,Q5 OFF ,Q6 OFF

Thanks

 

I find it a little confusing that the output is extracted from that point.

Why do you find it confusing? We need something more than that if we are going to try to clear up the confusion.

For the output to be equal to 1(high state) Q5 will always have to be on,right?

Correct.

I mean is not possible the output to be 1 if Q5 is off and Q6 is on rigth?

Correct.

Input A Input B
0 0

Q1 ON,Q2 OFF,Q3 OFF,Q4 OFF,Q5 OFF ,Q6 ON

If Input A being 0 results in Q1 being ON, then why would Input B being 0 result in Q2 being OFF. Does that make sense?

If Q1 is the only transistor (out of Q1 to Q4) that is ON, then how can any signal get to the gates of Q5/Q6?

For a digital CMOS circuit, functionally you treat a PMOS as ON if the gate voltage is LO and an NMOS as ON if the gate voltage is HI. But you have to have a path from the gate to a driving source (an input or a supply) that goes through gates that are ON.

 

Why do you find it confusing? We need something more than that if we are going to try to clear up the confusion.

It consfuses me that the output is extracted from the drains two transistors.If the transistor Q5 is on it will have current in the drain.And if only Q6 is on we dont have current in the drain?The output is not high because we don't have a path from the gate to a driving source (an input or a supply) that goes through gates that are ON(in the case i mentioned Q6),when Q5 is OFF?

If Q1 is the only transistor (out of Q1 to Q4) that is ON, then how can any signal get to the gates of Q5/Q6?

So if i have 0 0 in the input

Q1 ON-->Vgs<0

Q2 ON --> Vgs <0

Q3 OFF

Q4 OFF

Q5 OFF

Q6 ON--> Vgs>0



Input A Input B
0 1

Q1 ON,Q2 ON,Q3 OFF,Q4 ON,Q5 ON ,Q6 ON


Output = 1


Input A Input B
1 0

Q1 OFF

Q2 ON

Q3 ON

Q4 OFF,

Q5 OFF because Vgs=0v

Q6 ON

Output = 0 (this is not correct ,since this is a or gate.The state of Q5 will determine wheater the ouput is 1 or 0.

Q5 depends on the state of Q2 and Q3.

So if Q2 is ON and Q3 is ON this means that Q5 this means that Q5 will have +Vdd on the gate and on the source.Theferore Vgs=0V,so i dont understand how Q5 can be ON(since it will have to be because the circuit implements a OR gate).

Thanks

 

Good way to remember it is ...

OR (any 1 Gives a 1)
AND (all 1s give a 1)
Nand (all 0s gives a 1)

When you formally study this, this is how they teach it.

Write it out on paper 100 times and you never forget.

 

Good way to remember it is ...

OR (any 1 Gives a 1)
AND (all 1s give a 1)
Nand (all 0s gives a 1)

When you formally study this, this is how they teach it.

Write it out on paper 100 times and you never forget.

My question isnt't about that.What i want to know is how can transistor Q5 be ON when we have

Input A Input B

1 0

If Q2 is ON and Q3 is ON this means that Q5 this means will have +Vdd on the gate and on the source.
Theferore Vgs=0V,so i dont understand how Q5 can be ON

 

Sorry I read things quick and in part and make assumptions sometimes. I am on a smart phone too.

Your question is rather complex, and I do not have answers off the top of my head. Perhaps an expert or two can shed some light?

 

If [...] Q3 is ON this means that Q5 this means will have +Vdd on the gate and on the source.

If Q3 is on, the gate of Q5 is pulled to ground....

Q2 doesn't crate a path to +VDD since Q1 is off...

 

Is this configuration called a totem pole or something like this?

 

Is this configuration called a totem pole or something like this?

The totem pole term has much vagueness around it - some people having learned it to refer only to analog amplifiers and others to refer to any sort of push-pull arrangement, which is a preferred term.

But, yes, this can be a totem pole output...
http://en.wikipedia.org/wiki/Push%E2%80%93pull_output

 

Might be easier to go off truth tables than have scattered on and off this if that all over the place.

 

If Q3 is on, the gate of Q5 is pulled to ground....

Q2 doesn't crate a path to +VDD since Q1 is off...

Why is the gate of Q5 pulled to the ground?If Q3 is on won't we have current on the source of Q3?

 

Why is the gate of Q5 pulled to the ground?If Q3 is on won't we have current on the source of Q3?

who said current!? MOSFETs are voltage-controlled devices.

What is Vds for a saturated MOSFET?

 

who said current!? MOSFETs are voltage-controlled devices.

What is Vds for a saturated MOSFET?

Vds=Vgs-Vt,the n-channel pinches off at the drain and therefore there is no current at the drain?So this means that there is no current at the drain when the MOSFET is saturated?

Thanks

 

Vds=Vgs-Vt,the n-channel pinches off at the drain and therefore there is no current at the drain?So this means that there is no current at the drain when the MOSFET is saturated?

Thanks

Why are you concerning yourself with current? We are talking about what happens in a voltage-controlled device, however, there will be almost no current, aside from switching currents...

 

Why are you concerning yourself with current? We are talking about what happens in a voltage-controlled device, however, there will be almost no current, aside from switching currents...

Why is Q5 pulled to the ground?Q2 is off and therefore it isn't possible to have +Vdd in the gate of Q5,but how do i know is the gate of Q5 is conected to the ground?Because Q3 is ON and it creates a path to the ground for Q5 is that it?

Thanks

 

Why is Q5 pulled to the ground?Q2 is off and therefore it isn't possible to have +Vdd in the gate of Q5,but how do i know is the gate of Q5 is conected to the ground?Because Q3 is ON and it creates a path to the ground for Q5 is that it?

Thanks

Vds for a saturated transistor is ~= 0V... Vds for a transistor in cutoff is unbound...

 

Vds for a saturated transistor is ~= 0V... Vds for a transistor in cutoff is unbound...

So vds of Q3 is aprox 0 V and therefore since Q3 is ON there is path that conect the GATE of Q5 to the ground,rigth?

 

So vds of Q3 is aprox 0 V and therefore since Q3 is ON there is path that conect the GATE of Q5 to the ground,rigth?

allow me to rearrange your statement:

So, since Q3 is ON(and in saturation), Vds of Q3 is aprox 0V, therefore the GATE of Q5 is aprox 0V, with respect to ground.

 

allow me to rearrange your statement:

So, since Q3 is ON(and in saturation), Vds of Q3 is aprox 0V, therefore the GATE of Q5 is aprox 0V, with respect to ground.

What if the inputs are both equal to 1

Input A Input B
1 1

Output = 1

Q1 OFF,Q2 OFF,Q3 O3 ON,Q4 ON,Q5 ON ,Q6 OFF.Is that it ?

Thanks

 

What if the inputs are both equal to 1

Input A Input B
1 1

Output = 1

Q1 OFF,Q2 OFF,Q3 O3 ON,Q4 ON,Q5 ON ,Q6 OFF.Is that it ?

Thanks

Sounds like you've got it...however, you should learn to put your information into tables, it would help others know what you are attempting to say...