CMOS logic gate

Discussion in 'Homework Help' started by m_dic, Nov 8, 2005.

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  1. m_dic

    Thread Starter New Member

    Nov 8, 2005
    2
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    hey cud someone pls help me with this

    the question is :

    sketch a transistor level schematic for a single stage CMOS logic gate for the following functions

    Y= (ABC+D)'

    Y=(AB + (C.(A+B)))'

    i want to know how to connect the pmos and cmos gates in the pullup and pull down networks.

    hope someone helps me soon.
     
  2. Dave

    Retired Moderator

    Nov 17, 2003
    6,960
    143
    Please post replies in the active topic, here.

    Dave
     
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