CMOS Inverter

Discussion in 'General Electronics Chat' started by Mazaag, Feb 12, 2007.

  1. Mazaag

    Thread Starter Senior Member

    Oct 23, 2004
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    0
    Hi guys,
    question about the good ole CMOS Inverter.

    Why does increasing the value of the WIDTH of the PMOS (or NMOS) change the threshold voltage of the inverter ? I understand the varying the width changes the current through the transistor at a given Vov, but I don't understand why it shifts the Voltage Transfer Characteristics to the left or to the right.

    Thanks guys
     
  2. Dave

    Retired Moderator

    Nov 17, 2003
    6,960
    144
    The threshold voltage for any MOSFET is dependant on several parameters:

    - The zero bias threshold voltage
    - The body effect parameter
    - The surface potential parameter
    - The bulk-source voltage

    Changing the width of the MOSFET channel will have an effect on the above parameters in differing ways and consequently the threashold voltage.

    For a mathematical explanation refer to http://ece-www.colorado.edu/~bart/book/book/chapter7/ch7_4.htm

    The more common expression of the threshold voltage is:

    Vt = Vto + y(√(Vsb + 2φf) - √(2φf))

    Where:

    Vt - threshold voltage

    Vto - zero bias threshold voltage

    y - body effect parameter

    Vsb - source-bulk voltage

    2φf - surface potential parameter

    Dave
     
  3. Mazaag

    Thread Starter Senior Member

    Oct 23, 2004
    255
    0
    I may have not been too clear.

    I am referring to the threshold voltage of the INVERTER, as in, the value between VIL and VIH.

    Thanks
     
  4. Dave

    Retired Moderator

    Nov 17, 2003
    6,960
    144
    Apologies I misunderstood (read as misread) your question.

    What you are refering to is what is known as Beta Ratio Effects, i.e. the β ratio of the pMOS transistor to the nMOS transistor - βp/βn.

    Consider the case where βp = βn (note that μn ~ 2μp and hence Wp ~ 2Wn), then the ratio is 1 and the inverter threshold voltage is Vdd/2. It should be clear in this instance that for the CMOS inverter driving a capacitive load (as tends to be the case) both the pMOS and nMOS transistors charge and discharge in equal times meaning that the inverter has equal sourcing and sinking capabilities to the load.

    Now if a situation arises such that βp =/ βn then we have what is known as a skewed inverter. In this instance, one of the β values for one of the transistors is greater than the other meaning that that particular transistor is "stronger", i.e. it has greater load driving capabilities. The terminology for an inverter where βp > βn (and βp/βn > 1) is a hi-skewed inverter, and the terminology for an inverter where βn > βp (and βp/βn < 1) is a low-skewed inverter. It should be no surprise that the terminology for an inverter where βn = βp (and βp/βn = 1) is an un-skewed inverter.

    Consider the hi-skewed inverter: from the above discussion this has a stronger pMOS transistor and we would expect the input threshold voltage to be greater than for an un-skewed inverter and hence the output voltage would be greater also, i.e. greater than Vdd/2 - this is characterised by a rightwards movement of the inverter transfer characteristic. The converse is true for a low-skewed inverter, which has a weaker pMOS transistor and hence the input threshold voltage is lower, leading to a lower output voltage than Vdd/2 - this is characterised by a leftwards movement of the inverter transfer characteristic.

    Finally from a practical perspective, the width variable of β is often used to skew the β-ratio because it maintains a minimum length which is critical for speed.

    Dave
     
    henry2016 likes this.
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