CMOS Inverter design

Discussion in 'General Electronics Chat' started by kdillinger, Jul 4, 2010.

  1. kdillinger

    Thread Starter Active Member

    Jul 26, 2009
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    I am trying to simulate a basic CMOS inverter. I am trying to target a 2.5V for my midpoint voltage but it is shifted about 400mV.
    I have attached my circuit and calculations for kp, kn, W/L, Vtn, Vtp, and Vmid. It all works out on paper, just not in the simulation.
    There are other parameters in the Level 1 Spice models that I cannot zero out because I get floating point errors if I do.
    Any ideas?
     
  2. Ghar

    Active Member

    Mar 8, 2010
    655
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    How do you know you're using the right values in the calculation?
    Can you modify the spice models?
     
  3. SgtWookie

    Expert

    Jul 17, 2007
    22,182
    1,728
    Looks like you have a voltage controlled voltage divider with no feedback, and no way to determine what the Vgs threshold is for the MOSFETs.

    Without a feedback loop, you have no way to control the output voltage.

    Without switched capacitors or switched inductors, you have no control over power dissipation in the FETs.

    Go fish!
     
  4. Ghar

    Active Member

    Mar 8, 2010
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    This is meant to be a logic inverter.
     
  5. SgtWookie

    Expert

    Jul 17, 2007
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    Ahh, OK.

    In that case, the output will be indeterminate if you are in the "forbidden zone"; ie: in between a logic 1 and a logic zero.

    However, it's easier for electrons to flow than holes. So, if you use a P-channel FET that's complementary to an N-channel FET in the arrangement shown, you're likely to be showing a lower output voltage than you would expect.

    Use positive feedback to create a Schmitt trigger. That way you'll avoid the indeterminate zone.
     
  6. vustudent

    Active Member

    Mar 11, 2009
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    Did you make your pmos 2 times wider than your nmos?

    Since holes have lower mobility than electrons, so you will have to compensate by making your pmos wider, in order to have balance on and off for your inverter.
     
  7. Ghar

    Active Member

    Mar 8, 2010
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    His calculations show that he wants the PMOS 2.5 times larger than the NMOS.
    The transfer curve implies the PMOS is actually too large compared to the NMOS...
     
  8. kdillinger

    Thread Starter Active Member

    Jul 26, 2009
    141
    3
    2.5 times wider to be exact. Wn is 4um and Wp is 10um. They both have the same length.

    This is a cookbook example for a symmetrical inverter. Known variables are Vdd, Vtn, Vtp, Wn, Ln, Lp, k'n, and k'p.

    Kn, kp, and Wp need to be determined before the midpoint voltage, Vm, can be calculated as shown in my Calc.pdf.

    So when I edit the Level 1 spice model there are several parameters that are populated but are not involved in the above calculations, so I do not know if they are affecting the midpoint voltage. If I reduce them to 0 then I receive a 'divide by 0' error.
     
  9. Ghar

    Active Member

    Mar 8, 2010
    655
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    Post your Spice model?
     
  10. kdillinger

    Thread Starter Active Member

    Jul 26, 2009
    141
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    I don't know how to export the models from TINA. They are existing Level 1 models with all sorts of variables to tweak. So I have to do it the old fashioned way:

    pMOS:
    vto:-1
    kp:80u
    phi:600m
    is:10f
    N:1
    pb:800m
    mj:500m
    tox:100n
    uo:600
    tpg:1
    af:1
    l:2u
    w:10u

    nMOS:
    vto:1
    kp:80u
    phi:600m
    is:10f
    N:1
    pb:800m
    mj:500m
    tox:100n
    uo:600
    tpg:1
    af:1
    l:2u
    w:4u

    From TINA's help file and other sources around the web:

    IS: bulk p–n saturation current
    N: bulk p–n emission coefficient
    Mj: bulk p–n grading coefficient

    af: Flicker noise exponen
    t
    PB: Bulk p-n potential

    TPG: Gate material type


    I am no device physicist so I have no idea what these parameters control.
     
  11. Ghar

    Active Member

    Mar 8, 2010
    655
    72
    Both the NMOS and PMOS have the same kp value of 80u.
    kp is where the carrier mobility shows up which is the reason for PMOS having to be larger than NMOS. By using the same value you make them perform equally well.

    Try scaling them to what you used in your calculation:
    40u and 16u

    Here's a more relevant link:
    http://wiki.xtronics.com/index.php/Tina#MOSFET_model_parameters
     
    Last edited: Jul 6, 2010
  12. kdillinger

    Thread Starter Active Member

    Jul 26, 2009
    141
    3
    According to Digital Integrated Circuits by DeMassa kp of the pMOS should be equal to kn of the nMOS in a symmetrical inverter.

    Attached are the new values you asked me to try and the shift is even worse.
     
  13. Ghar

    Active Member

    Mar 8, 2010
    655
    72
    There are two varieties that are often used... you're even using them in your calculation, kn and kn'.

    One is just the other multiplied by W/L.
    You make kn' W/L = kp' W/L
    If kn' = kp' then you don't need to change the W/L
    I believe that in this case the model parameter called kp is your kp'

    Are you sure you put the correct values in, regarding NMOS vs PMOS?
    PMOS should be 16u and NMOS should be 40u.
    That curve suggests PMOS is even stronger than before.

    This is what I think happened originally...

    kp = 10/2 * 80u = 400u
    kn = 4/2 * 80u = 160u
    Vth = 2.84 V

    And your change:
    kp = 10/2 * 40u = 200u
    kn = 4/2 * 16u = 32u
    Vth = 3.14

    Those fit fairly well with your plots...

    Alternatively leave what you had original (kp 80u for both) but make both have W = 10u and see what happens. I suspect you'd have a symmetric inverter then but it wouldn't fit your calculations.
     
  14. kdillinger

    Thread Starter Active Member

    Jul 26, 2009
    141
    3
    No, that didn't work. I doubled checked the calculations and my entries in the models.

    I think it has to do with the Vt's of the device, but I am not sure. There are several parameters that go into the definition of Vt, but it does not look like they are involved in the Level 1 model so it is hard to say why the transfer graph is shifted.

    I changed the Vt of the pMOS and nMOS to be 2.5V which is the same as the calculated VM of the inverter. See attached.

    Couldn't ask for a more text book transfer function than that! But because it is ideal, I still wonder what I missed.
     
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