cmos design

Thread Starter

vead

Joined Nov 24, 2011
629
when designer design new circuit, they think whats the requirement

step I
1)power dissipation should be less
2)raise time and fall time should be less
3)propagation delay time should be less
4)size should be small as possible

step II

1) how can we reduce power dissipation in cmos circuit?

- we have to decrease voltage or current in circuit
- we have to decrease resistance in circuit

2) how can we reduce raise time and fall time?
-which parameter depend on raise and fall time
 

olvine

Joined Mar 10, 2014
99
Rise and fall time of transistors depends on the internal capacitances and it's solely dependent on the construction.
P.S I am talking about transistor. Not about the whole circuit
 

Thread Starter

vead

Joined Nov 24, 2011
629
capacitance is charged and discharged when capacitor is charged can we say its raise time and when capacitor is discharged can we say its fall time
 

Thread Starter

vead

Joined Nov 24, 2011
629
Q1) how can we reduce power dissipation in cmos circuit?

Q2)why nmos and pmos have different W/L ratio
to obtain the same raise time and fall time in cmos circuit , the w/l ratio of Pmos should be double then nmos
 

crutschow

Joined Mar 14, 2008
34,285
Q1) Reduce the supply voltage and/or the feature size (which reduces parasitic capacitance)

Q2) Because the P-channel carrier mobility is less then the N-channel mobility so the P-channel devices must be larger to have the same gain.
 

Thread Starter

vead

Joined Nov 24, 2011
629
what should we do to achieve 215 ps delay
this is just example for my understanding

I think I need following thing but its not all I am missing some
1.power supply
2.threshold voltage for nmos
3.threshold voltage for pmos
4.load capacitance

please anyone tell me what should we do to achieve 215 ps delay
 

crutschow

Joined Mar 14, 2008
34,285
what should we do to achieve 215 ps delay
this is just example for my understanding

I think I need following thing but its not all I am missing some
1.power supply
2.threshold voltage for nmos
3.threshold voltage for pmos
4.load capacitance

please anyone tell me what should we do to achieve 215 ps delay
Whether you can get that low a delay or not depends upon the CMOS fabrication process parameters of the manufacturer of the chip.
 

Thread Starter

vead

Joined Nov 24, 2011
629
Whether you can get that low a delay or not depends upon the CMOS fabrication process parameters of the manufacturer of the chip.
1.power supply
2.threshold voltage for nmos
3.threshold voltage for pmos
4.load capacitance

If we know the above v alues. can we achieve desired delay time. or I need to know another value
 
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