cmos design

Discussion in 'General Electronics Chat' started by vead, May 20, 2014.

  1. vead

    Thread Starter Active Member

    Nov 24, 2011
    621
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    when designer design new circuit, they think whats the requirement

    step I
    1)power dissipation should be less
    2)raise time and fall time should be less
    3)propagation delay time should be less
    4)size should be small as possible

    step II

    1) how can we reduce power dissipation in cmos circuit?

    - we have to decrease voltage or current in circuit
    - we have to decrease resistance in circuit

    2) how can we reduce raise time and fall time?
    -which parameter depend on raise and fall time
     
  2. olvine

    Member

    Mar 10, 2014
    99
    0
    Rise and fall time of transistors depends on the internal capacitances and it's solely dependent on the construction.
    P.S I am talking about transistor. Not about the whole circuit
     
  3. vead

    Thread Starter Active Member

    Nov 24, 2011
    621
    8
    capacitance is charged and discharged when capacitor is charged can we say its raise time and when capacitor is discharged can we say its fall time
     
  4. crutschow

    Expert

    Mar 14, 2008
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    3,243
    Depends upon whether the stay capacitance is to ground or to the V+ supply.
     
  5. vead

    Thread Starter Active Member

    Nov 24, 2011
    621
    8
    what is load capacitance in cmos circuit
     
  6. crutschow

    Expert

    Mar 14, 2008
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    That would seem to be self explainitory. :rolleyes: It's the capacitance on the circuit output due to various stray and parasitic load and interconnect capacitances.
     
  7. vead

    Thread Starter Active Member

    Nov 24, 2011
    621
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    Q1) how can we reduce power dissipation in cmos circuit?

    Q2)why nmos and pmos have different W/L ratio
    to obtain the same raise time and fall time in cmos circuit , the w/l ratio of Pmos should be double then nmos
     
  8. crutschow

    Expert

    Mar 14, 2008
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    Q1) Reduce the supply voltage and/or the feature size (which reduces parasitic capacitance)

    Q2) Because the P-channel carrier mobility is less then the N-channel mobility so the P-channel devices must be larger to have the same gain.
     
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  9. vead

    Thread Starter Active Member

    Nov 24, 2011
    621
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    you mean we need to reduce transistor size and supply voltage
     
  10. vead

    Thread Starter Active Member

    Nov 24, 2011
    621
    8
    what should we do to achieve 215 ps delay
    this is just example for my understanding

    I think I need following thing but its not all I am missing some
    1.power supply
    2.threshold voltage for nmos
    3.threshold voltage for pmos
    4.load capacitance

    please anyone tell me what should we do to achieve 215 ps delay
     
  11. crutschow

    Expert

    Mar 14, 2008
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    3,243
    Whether you can get that low a delay or not depends upon the CMOS fabrication process parameters of the manufacturer of the chip.
     
  12. vead

    Thread Starter Active Member

    Nov 24, 2011
    621
    8
    1.power supply
    2.threshold voltage for nmos
    3.threshold voltage for pmos
    4.load capacitance

    If we know the above v alues. can we achieve desired delay time. or I need to know another value
     
  13. vead

    Thread Starter Active Member

    Nov 24, 2011
    621
    8
    please help me someone
     
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