CMOS Comparator for PWM

Discussion in 'The Projects Forum' started by chintook, Jan 27, 2014.

  1. chintook

    Thread Starter New Member

    Jan 27, 2014
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    I am trying to understand how I can make a CMOS comparator that will be used for PWM.

    I have a triangle wave that will pass through one input of the comparator.

    The second input will be reference voltage. The width of the pulse will be smaller when the reference voltage is higher.

    The closer the reference voltage is to the tip of the triangle wave the smaller it will be. I understand this concept of PWM.

    I have a bunch of CD4007 IC's that I want to use to accomplish this.

    Can anyone lend a hand in how I should approach doing this?
     
  2. crutschow

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  3. Alec_t

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    You can use a CMOS logic gate . Use summing resistors to add the triangle voltage to the reference voltage and apply the sum to the gate input. When the sum reaches the gate threshold the gate trips. PWM duty cycles from 0% to 100% are achievable.
    A CD40106 or CD4093 gate gives a well-defined threshold, but because of the Schmitt hysteresis the duty cycle range is reduced.
     
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  4. crutschow

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    That's an interesting idea. I hadn't thought about adding the two voltages together and using a fixed trigger voltage but it should work the same.
     
  5. chintook

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    Jan 27, 2014
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    Wow, never though of this. seems like a pretty simple design compared to what I have found.

    I found this comparator circuit that is using CD4007 and I tested it out on spice and it's working. I'm just not sure of the concept behind it.

    I used a sawtooth that has a really linear charging period and it's working great.

    You have any idea about how this works?
     
  6. crutschow

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    That circuit is a discrete implementation of a CMOS differential amplifier used as an analog comparator. In that circuit when Vsaw is higher than Vin the output goes to a high voltage.

    Below is a PWM simulation using Alec's idea with a simple CMOS inverter circuit.

    PWM-CMOS.gif
     
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  7. chintook

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    Jan 27, 2014
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    Wow I am going to try that out. Thanks for showing me what that it could be done. Its nice to learn new methods. I gotta open up my mind here haha.

    However, I am still curious about the circuit I posted earlier.

    It seems like PMOS transistors M9 and M1, and the NMOS M3 and M4 form a current mirror.

    So we have equal currents going down into the drain of M3 and M4. While the Sawtooth input and Vin are controlling those NMOS transistors at the gates.

    I am not sure exactly what is going on after this at the bottom left side of the circuit. The source of M3 and M4 are joined and their current travels down to the drain of M6?

    I would appreciate if you could help explain this part to me!

    Thanks again!
     
  8. crutschow

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    Here's an explanation that should help.
     
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  9. chintook

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    Jan 27, 2014
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    Thanks! Time to read up.

    Ill be back when I have questions!

    Thanks a bunch crutschow
     
  10. Alec_t

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    Last edited: Jan 29, 2014
  11. chintook

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    Jan 27, 2014
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    In the lab report it describes "passive series elements" are these the two matches PMOS transistors M9 and M1 that make up the current mirror?
     
  12. crutschow

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    No. Those are generally resistors. Capacitors and inductors are also passive elements. Transistors are "active" elements.
     
  13. chintook

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    Jan 27, 2014
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    At the bottom of the image I had attached previously there are the transistors M6 and M5. I believe that M6 is acting as a current source so that the currents will flow through M3 and M4 evenly? is this correct? If so then what is M5 used for?

    Are the 3 1K resistors just there to bias M5 and M6?

    Thanks
     
  14. Alec_t

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    The resistors set the gate voltage, hence drain current, of M5. Since M5, M6 and M10 are of identical construction and have the same gate voltage the drain currents of M6 and M10 will 'mirror' the current of M5. M9 and M1 are similarly in a current mirror arrangement.
     
  15. chintook

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    Jan 27, 2014
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    So does this mean that the transistors M5, M6, and M10 are always operating in the saturation region?

    I am just a little confused about the bottom two transistors, as in why they are part of the circuit. M6 is there to drain the current from M3 and M4 it seems?
     
    Last edited: Feb 4, 2014
  16. Alec_t

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    Yes.
    M3 and M4 form a 'long-tail pair' and M6 is operating as a constant-current sink in the tail.
     
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  17. chintook

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    Jan 27, 2014
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    Hey guys,

    Yeserday I tested out the circuit on a breadboard in the lab. I was able to get the PWM working. I have an issue though, I have 4 different voltages powering my circuit. Vdd is at 10v, Vss is at -3 volts and these two voltages come from two different power supplies (same model). However at my output there is a single CMOS inverter which I wanted to produce a pulse from 0 to 5 volts so for this inverter I used a different Vdd2 of 5 volts and Vss of GND. All of these voltages plus an input voltage (1 - 10 volts) for the other half of the differential amplifier will require me to use 2 to 3 power supplies in the lab. My question is how can I share a common through these power supplies? or do I need to?

    The power supplies I am using are these
    http://www.home.agilent.com/en/pd-8...6v-25a-20v-05a?nid=-35678.384187&cc=US&lc=eng

    Agilent E3630A 35 W Triple Output, 6V, 2.5A & ±20V, 0.5A
     
  18. Alec_t

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    Why can't you use just a single supply for everything?
     
  19. chintook

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    Jan 27, 2014
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    How would I be able to do that?
     
  20. Alec_t

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    Couldn't you have Vss=0, Vdd=12, and a potential divider (instead of the inverter) on the output to drop 12V down to 5V?
     
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