CMOS circuit question

Discussion in 'Homework Help' started by vg19, Nov 21, 2006.

  1. vg19

    Thread Starter New Member

    Nov 3, 2004

    I am having trouble with the attached CMOS circuit question. The only way I see about doing it is getting the truth table and listing each transitor and its corresponding state. However, this looks like it will take a long time...Is there another way to determine the boolean expression?

  2. Papabravo


    Feb 24, 2006
    It's a twinkling of the eye compared to the time it takes to earn a degree.
  3. Dave

    Retired Moderator

    Nov 17, 2003
    For some reason I keep getting errors on the download, could you upload the circuit and any of your workings as a JPEG?

  4. n9352527

    AAC Fanatic!

    Oct 14, 2005
    For a standard gate, where the pull-down circuit is the series-parallel complement of the pull-up circuit, e.g. If each NMOS (or sub-circuit) associated with A and B at the pull-down are connected in series then each PMOS (or sub-circuit) associated with A and B at the pull-up must be connected in parallel. Then the invert of function (F') can be obtained quickly by OR-ing each parallel NMOS (or parallel sub-circuit) and AND-ing with the series NMOS (or series sub-circuits thereof).

    In your example above, by inspection we can see that the NMOS connected to C is in series with the parallel sub-circuit of NMOSs connected to A and B. So the function is F' = (A + B)C. There is also an inverter at the output, so the overall function is F = (A + B)C, which is equivalent to F = AC + BC.

    It does seem complicated (and I made it to sound more complicated :D), but once you've done a few examples you'll find that it is quite easy and intuitive. Just make sure first that the pull-up and the pull-down circuits are series-parallel complement of each other.
  5. Dave

    Retired Moderator

    Nov 17, 2003
    Finally got it working - must have been a connection issue.

    I concur with n9352527's assessment of the circuit. You can verify the boolean equation by tracing the route to ground from the input of the inverter: you can either go through [A and C] or [B and C]. From this you can see an important characteristic of CMOS technology; CMOS is by its very structure inverting. Therefore the boolean function at the input to the inverter is F(A,B,C) = NOT[A.C + B.C]. The inverter makes the function F(A,B,C) = NOT[NOT[A.C + B.C]] or simplified F(A,B,C) = A.C + B.C.

    So you can often assess the boolean function through merely analysing the pull-down path and remembering that CMOS provides an inverting output. Provided the circuit is proper static or dynamic CMOS then this method is valid. (In fact this method is also valid for pseudo-nMOS which is very similar in principle to CMOS).