CMOS AND gate

Discussion in 'General Electronics Chat' started by tejasdj12, Oct 25, 2012.

  1. tejasdj12

    Thread Starter New Member

    Jul 11, 2010
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    Hello Guys,
    This should be my first thread. I'm a Electronics and Telecom student. Electronics is my current hobby. I'm quite new to some circuit concepts.
    Today, I was playing with MOSFETs and designed an AND gate with it (Circuit I). After that, I googled and found another circuit (Circuit II). Is it fine that I don't add another pair of MOSFETs (MOSFETs 5 and 6 in Circuit II)? Or are there any sourcing or sinking problems with Circuit I?
    [​IMG]
     
  2. Ron H

    AAC Fanatic!

    Apr 14, 2005
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    In circuit 1, your output is connected to the power supply. How is the output going to change?
    Circuit 2 is a NAND gate. You have to add an inverter (NOT gate) to the output to make it an AND gate.
     
  3. JMac3108

    Active Member

    Aug 16, 2010
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    You have your MOSFET symbols reversed. The IRF530 is an N-chan, but you show it as a P. The IRF9530 is a P-chan, but you show it as an N. You should probably redraw the circuit correctly so its better understood so people can comment on it.
     
  4. tejasdj12

    Thread Starter New Member

    Jul 11, 2010
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    Even if one of the input goes LOW, at least one MOSFET will start conducting. It will be a least resistive path (I think). So current should flow through either of the MOSFETs when input is LOW
     
  5. tshuck

    Well-Known Member

    Oct 18, 2012
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    Circuit1 is not CMOS. CMOS stands for complementary metal oxide semiconductor, what you have isn't complementary, add you have only one type MOSFET.

    Also, circuit two is an AND gate, but the PMOS and NMOS positions are flipped from their usual locations, NMOS on bottom when drawn....
     
  6. takao21203

    Distinguished Member

    Apr 28, 2012
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    You'd get such problems if you build larger circuits, and use higher frequencies. Of course the circuits do not work if they are directly built as shown. Maybe OP is aware of this.
     
  7. tejasdj12

    Thread Starter New Member

    Jul 11, 2010
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    Sorry, the editor I used was messed up I think. Here's the new circuit diagram:
    [​IMG]

    And I was asking why Circuit I would fail? When both inputs for Circuit I are HIGH, both Q5 and Q6 will act as open and Y will be HIGH. In case any of the inputs are LOW, current would directly sink through one of the MOSFETs. So Y will be LOW. Then is there any need to add the additional two n-MOSFETs in Circuit II?

    @takao21203 Which problems? Can you elaborate a bit
     
  8. takao21203

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  9. JMac3108

    Active Member

    Aug 16, 2010
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    In circuit I you need to flip your MOSFETS over so that the source is connected to VDD. Then, a low at the input turns on the FET,a high keeps it off.

    BUT, the circuit won't work anyway. When you turn on Q5 or Q6 you short VDD directly to ground. Bad idea :rolleyes:. You need to limit the current, maybe add a pull-up resistor in series with VDD?
     
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  10. tejasdj12

    Thread Starter New Member

    Jul 11, 2010
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    Yeah, this was just an example. Anyways, thanks a lot for your help!!
     
  11. Ron H

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    In either case, you can't get the output to change when it is tied to a supply rail, either VDD or GND.
     
  12. takao21203

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    Apr 28, 2012
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    Such an AND gate would rather be an emulation of a TTL circuit (i.e. using a resistor to get the voltage drop). CMOS OR is based on a CMOS NOR, and a CMOS inverter.

    There are some good websites, but you have to dig 50 or 100 links, skipping the tuna encyclopedia websites (means spawned from Wikipedia, which isn't totally wrong as a starting point, or containing more adverts than information, if any).

    CMOS is the main search word, you need to add some additional terms, like gate, logic, mosfet, digital, simulation, etc.
     
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