Here two clocks are used CP2 for loading parallel data's and CP1 for loading data serially by shifting .Why two clocks are being used here.Thank you in advance.

 

Hello Bhuvanesh
I guess because it is necessary for the architecture of the device.
Or, how would you do with only one clock ?.

 

Your circuit has some errors, the correct circuit is here.
Please check page 2 and using 1 and 0 to the inputs, maybe you will find something.

 

Hello ScottWang

I have rotated the bhuvanesh’s image.
I only encounter an error.
However, everything else seems the same; bhuvanesh image and the image in Motorola and Texas Instruments data sheets.

The reason of why two clocks I do not know. Would have to ask the IC designer.
It may work with only one input Clock. But would not be 74LS95.
As shown in the picture: X 74LS95 Shift Register Single clock.png attached.

 

Hi,
This clip from a data book explains the clocks in more detail.

 

thanks.i learned gating clock produce propagation delay,doesn't it?

 

Hello bhuvanesh

You say:
-I Learned clock gating occurs propagation delay, doesn't it ?-

Yes, that's right, all the signals, once entering the IC’s, have a propagation delay time.

 

Hi,
This clip from a data book explains the clocks in more detail.

do u have circuit for the given explanation ?

 

hi,
Look at this link for a Lab exercise
http://www2.hawaii.edu/~jrand/ElectricalEngineering/6 - ShiftRegister/

and page #2 of the d/sheet

Eric