As one new to flip flops and logic design I have a question on the clock pin. I understand that most work on the rising edge, but does it need to be a pulse? In an asynchronous system, can the rising edge just be a high from a proceeding sequence?
Yes, generally set and reset signals are asynchronous (independent of the clock input) and are active at a given logic level, the same as logic gates.Not only do D-type flip-flops have an edge-triggered clock input, interestingly some have set (preset) and reset (clear) inputs which are level-sensitive rather than edge-triggered.
This ties in with another thread about what is a CLOCK.Thanks for all the answers. I need to be using CD4xxx chips for this. Alec_t and crutschow must be psychic, my next question was about the set/reset pins on the 4013. Can they be a pulse? Or are they strictly level? Nothing on the data sheets or any literature I can find says one way or the other.
The 7474 D-type flip-flop is a positive edge-triggered flip-flop. The outputs will change shortly after (6ns) following a low-to-high transition of the CLOCK input. The D-input must be set up prior to the low-to-high transition of the CLOCK input.The last few days have my brain ready to explode and my eyes tired from reading about this stuff. The dreaded "metastable" is what I'm trying to avoid. Mr.Chips, isn't the 7474 a falling edge triggered chip? Instead of a rising edge like most are?
What you have created is a monostable circuit using a differentiator.I did manage to find a simple way to change a level signal to a pulse using a Schmitt trigger, resistor and cap though.
No. You can use a pulse on the S or R input. When the pulse level reaches the Hi value the action will occur. But the pulse edge steepness isn't critical, as it would be for the CLK input.So you guys are saying that a pulse will not make a lasting change on set or reset?
As I think you now understand, the two ways a digital circuit can respond are edge-triggered or level triggered. Neither one has a specific time that it has to be high (or low depending upon the "true" level for the circuit) , other than the minimum for the circuit to respond to the signal (as detailed in the data sheet for the particular circuit).Thanks guys, how you guys explained the S or R pin is how I thought it worked before this thread. Then here it was mentioned that S&R were level not pulse switched. So I then thought that meant, "level had to be held" to change output.
I tried to give you a picture of the difference between a "level" and a "pulse" but I guess it didn't work.Thanks guys, how you guys explained the S or R pin is how I thought it worked before this thread. Then here it was mentioned that S&R were level not pulse switched. So I then thought that meant, "level had to be held" to change output.
If you're designing an asynchronous system, you wouldn't use a clock.In an asynchronous system, can the rising edge just be a high from a proceeding sequence?