Clock pin on logic chip(another of my million dumb questions)

Discussion in 'General Electronics Chat' started by shortbus, Apr 24, 2015.

  1. shortbus

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    As one new to flip flops and logic design I have a question on the clock pin. I understand that most work on the rising edge, but does it need to be a pulse? In an asynchronous system, can the rising edge just be a high from a proceeding sequence?
     
  2. Papabravo

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    Yes it can be just an edge. The flip-flop only responds to the edge of the clock, and not the level. You must of course take account of the required setup and hold times. What are those you ask? The setup time is the amount of time prior to the clock edge that the data must be stable and unchanging. The hold time is the time after the clock edge that the data must remain stable and unchanging. Hold times can be close to zero, but setup times cannot. As always check the datasheet for details. And for your second million questions you should research metastability.
     
  3. MrChips

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    It depends.

    Some circuits are edge triggered, such as 7474 D-type flip-flop.

    7476 is a master-slave J-K flip-flop. The inputs are latched on the rising edge and the outputs are updated on the falling edge.
     
  4. Alec_t

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    Not only do D-type flip-flops have an edge-triggered clock input, interestingly some have set (preset) and reset (clear) inputs which are level-sensitive rather than edge-triggered.
     
  5. dl324

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    Hi shortbus,

    No, clock doesn't need to be a pulse, and yes, it can be a rising edge from some other logic.

    If you're ORing signals to generate a clock, you would have to convert all of the signals being ORed to pulses; otherwise, any HIGH input would prevent any other rising input from being passed to the clock input. If you don't want to bother with a one shot, you could use a differentiator (resistor and capacitor).
     
  6. crutschow

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    Yes, generally set and reset signals are asynchronous (independent of the clock input) and are active at a given logic level, the same as logic gates.
     
  7. shortbus

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    Thanks for all the answers. I need to be using CD4xxx chips for this. Alec_t and crutschow must be psychic, my next question was about the set/reset pins on the 4013. Can they be a pulse? Or are they strictly level? Nothing on the data sheets or any literature I can find says one way or the other.

    The last few days have my brain ready to explode and my eyes tired from reading about this stuff. The dreaded "metastable" is what I'm trying to avoid. Mr.Chips, isn't the 7474 a falling edge triggered chip? Instead of a rising edge like most are?

    I did manage to find a simple way to change a level signal to a pulse using a Schmitt trigger, resistor and cap though.
     
  8. crutschow

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    The FF will stay in the Set or Reset state as long as their respective inputs are at a logic true state.
    So they need a pulse to return the inputs to a false state if you want the FF to do anything else.
     
  9. MrChips

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    This ties in with another thread about what is a CLOCK.

    What is a pulse?

    A pulse is an edge (or transition), followed by a level, followed by another edge.
    An edge or transition can be either LOW-to-HIGH or HIGH-to-LOW. For obvious reasons one follows the other. That is, you cannot have two LOW-to-HIGH transitions in succession without an intervening HIGH-to-LOW transition.

    It can also be considered a level, followed by a level of the opposite logic level, followed by a level at the original level.

    So how do SET/RESET inputs work? These are LEVEL sensitive, ACTIVE-HIGH. That is a high input will activate the function.
    An obvious question is what happens if both SET and RESET are activated with HIGH inputs. The result at the outputs will depend on the internal design of the flip-flop. You can assume that is not recommended operation and should be avoided. When both SET and RESET signals are returned to logic LOW, there is no guarantee that the output of the flip-flop will be predictable. The outcome will be determine by internal propagation delays. We call this a "race problem" not to be confused with racial discord.

    The 7474 D-type flip-flop is a positive edge-triggered flip-flop. The outputs will change shortly after (6ns) following a low-to-high transition of the CLOCK input. The D-input must be set up prior to the low-to-high transition of the CLOCK input.

    What you have created is a monostable circuit using a differentiator.
     
  10. shortbus

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    Not trying to be combative just trying to understand. So you guys are saying that a pulse will not make a lasting change on set or reset? For the 4013 to work with the clock both set and reset must be held low, the way I understand it. If the S or R only works when held high, what good are they, if they disable the clock?

    I mean, if the S or R don't make a lasting change to the output state, why include them in the chip? I thought that's how you set them to the needed state on power up, with S or R. Sorry for being so dumb about this stuff.:(
     
  11. MrChips

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    You misunderstand.

    A flip-flop is a bi-stable device. It has two stable states.

    Apply a logic high to S-input and the Q-output goes high. Return the S-input to low and Q remains high.
    Apply a logic high to R-input and the Q-output goes low. Return the R-input to low and Q remains low

    This is true of an un-clocked S-R flip-flop.
    There is such a thing as a clocked S-R flip-flop which is a variation on the theme.
     
  12. Alec_t

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    No. You can use a pulse on the S or R input. When the pulse level reaches the Hi value the action will occur. But the pulse edge steepness isn't critical, as it would be for the CLK input.
     
  13. shortbus

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    Thanks guys, how you guys explained the S or R pin is how I thought it worked before this thread. Then here it was mentioned that S&R were level not pulse switched. So I then thought that meant, "level had to be held" to change output.
     
  14. Papabravo

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    Just to stir the pot a bit more. Some SR flip-flops will misbehave if you take both S and R active at the same time. To minimize the chances of this happening you would normally activate one or the other as appropriate, and then take the signal away after it had sufficient time to do it's work. You want to avoid an extremely short pulse, but you don't want the active level hanging around until the cows come home.
     
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  15. crutschow

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    As I think you now understand, the two ways a digital circuit can respond are edge-triggered or level triggered. Neither one has a specific time that it has to be high (or low depending upon the "true" level for the circuit) , other than the minimum for the circuit to respond to the signal (as detailed in the data sheet for the particular circuit).
     
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  16. MrChips

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    I tried to give you a picture of the difference between a "level" and a "pulse" but I guess it didn't work.

    How about: a pulse is three levels?

    LOW-HIGH-LOW

    or

    HIGH-LOW-HIGH

    Another way of putting this, a pulse is two transitions or edges

    and an edge is two levels.
     
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  17. shortbus

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    Anyone have an easy/simple edge detector circuit for the CD4xxx series of logic? The one I found was for the 74HC or 74HCT series.
     
  18. Brownout

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    If you're designing an asynchronous system, you wouldn't use a clock.
     
  19. Alec_t

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    What do you want to happen when you've detected the edge?
     
  20. shortbus

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    Brownout, I'm using the word, "clock", in the only way I know how to phrase it. As each section of the circuit finishes it's job the next flip flop will start the following sequence. In this project that "clock" signal is from a comparator reaching a certain voltage. This is why it is what I understand to be an asynchronous system. What else would it be called? There is no set timing to the circuit, if it takes 1 uSec or 10 uSec for each step that's what it takes. The flip flop is the only way I can see of doing it, to change from one operation to the next.

    Alec_T, it will just toggle from one state to the next. If I use the S - R pins to do it it gets to complicated. And using individual gates to make SR latches uses more IC's than the flip flops. The needed S or R will only be used at power up, to set "Q" at the correct state for the sequencing of the operations.

    You guy's forget I'm a beginner at this stuff, trying to do it the best I can.
     
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