Hi all. So I cam across this problem and i have no idea on how to approach. More than anything i would like to know what exactly they are asking me to do. I have not started this problem because i don't have a clue as to how. f someone could push me in the right direction so i can get started on this, that would be splendid. Draw a simplified circuit diagram of a clock network which clocks 5 functional units in a processor: adder, subtractor, multiplier, divider, square root. Each functional unit contains 48 flip-flops and must be designed so that its clock can be shut off to save power. The maximum fanout anywhere in the system is 4. The diagram need not show all parts of the clock system, but must include enough detail so that the structure and topology is clear.