Yes it is true. The basic circuit is called a phase locked loop. It starts with a high frequency Voltage Controlled Oscillator. The output is divided down and compared with a lower frequency crystal controlled oscillator. The phase difference is used to adjust the VCO up or down until the phase coming out of the divider is equal to the phase of the reference oscillator.hmm...
so i guess i would need an oscillator nonetheless.
for some other forums i post reagrding clock frequency, i have been getting feedbacks that a crystal oscillator can generate a frequency thta is higher than its rated value?
is it true or have i misunderstood their term of dividing the frequency down?
A voltage controlled oscillator is also known as a voltage to frequency converter. You increase the control voltage and the frequency goes up. Conversely you decrease the voltage and the frequency goes down.So if i am usign a Virtex 5 FPGA board, which has a on-board oscillator of 100MHz, but my design is able to run at 130MHz, my final controller will be able to perform at 130MHz?
And can you elaborate more on the Voltage Control Oscillator?
It is still a vague idea to me.
Thanks