Clock generation using VHDL

Discussion in 'Programmer's Corner' started by dumindu89, Sep 17, 2012.

  1. dumindu89

    Thread Starter Member

    Oct 28, 2010
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    Hi!
    Is it possible generate a clock signal (let's say 100 kHz clock)just by using a VHDL code without taking any external inputs?

    How can I write such a VHDL program?
     
  2. guitarguy12387

    Active Member

    Apr 10, 2008
    359
    12
    Technically you can use a ring oscillator circuit in VHDL. What is your application? Are you targeting an FPGA?
     
  3. dumindu89

    Thread Starter Member

    Oct 28, 2010
    113
    0
    Application: Reference clock frequency for the Digital Phase locked loop.

    Yep, I am targetting an FPGA.
     
  4. kubeek

    AAC Fanatic!

    Sep 20, 2005
    4,670
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    Might be possible, but the frequency will be quite unpredictable. Better use external crystal or oscillator and divide from there.
     
  5. guitarguy12387

    Active Member

    Apr 10, 2008
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    12
    I agree with Kubeek. Don't use this circuit for an FPGA especially. Routing differences alone will cause changes in frequencies.

    Use an external oscillator.
     
  6. WBahn

    Moderator

    Mar 31, 2012
    17,737
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    If it's targeting an FPGA, then you have to be really careful since FPGA logic is implemented in lookup tables, which are intrinsically glitchy.

    Most FPGAs have an internal RC oscillator, used for loading the configuration data from a ROM of some flavor, but you may or may not be able to access it internally and you may or may not be able to keep it running once the configuration is complete. Even if you can, it is going to be a really poor reference, both in terms of accuracy and stability.

    Use a decent crystal-based oscillator (or better, depending on your needs).
     
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