Clock fail detection circuit

Discussion in 'Homework Help' started by ashu123, May 30, 2015.

  1. ashu123

    Thread Starter New Member

    May 30, 2015
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    Can anybody help me design a clock fail detection cicuits without using delay lines.
    I came across the attached circuit which can detect the clock failure of a high frequency clock used as clock1 with the help of a good low frequency clock named clock2.
    My doubt is whether i can detect the failure of the low frequency clock with the help of a good high frequency clock?
    I have attached waveform of the below circuit and my requirement is the reverse.
    Pls help
     
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  2. JoeJester

    AAC Fanatic!

    Apr 26, 2005
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    are you constrained in any manner on your design?

    If you are not, search for Application Note 170 from Phillips Semiconductors. The 555 timer can be a missing pulse detector.
     
  3. ashu123

    Thread Starter New Member

    May 30, 2015
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    I am planning to use this along with adpll. So my input frequency(clock1) can vary between 61khz to 43Mhz and clock2 is 250mhz.
    Also i dont want to use a frequency divider to divide the 250mhz because to match with my input i may need large dividers.
     
  4. ashu123

    Thread Starter New Member

    May 30, 2015
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    0

    I am planning to use this along with adpll. So my input frequency(clock1) can vary between 61khz to 43Mhz and clock2 is 250mhz.
    Also i dont want to use a frequency divider to divide the 250mhz because to match with my input i may need large dividers. I need to code the design in verilog hdl
     
  5. JoeJester

    AAC Fanatic!

    Apr 26, 2005
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    61 kHz through 43 MHz and clock 2 at 250 milliHertz?
     
  6. ashu123

    Thread Starter New Member

    May 30, 2015
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    61Khz to 43Mhz and 250Mhz
     
  7. JoeJester

    AAC Fanatic!

    Apr 26, 2005
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    If your planning on using TTL devices, you know 41 MHz is outside their operating range ... and so is 250 MHz.
     
  8. ashu123

    Thread Starter New Member

    May 30, 2015
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    I want to code such a circuit in verilog hdl and simulate it. I have attached a similar circuit in thread 1
     
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