Clock Divider

Discussion in 'General Electronics Chat' started by imzack, Nov 10, 2010.

  1. imzack

    Thread Starter Active Member

    Nov 3, 2010
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    I need to make a clock divider in VHDL.
    I am given a clock of 50MHZ
    and i need to convert it to 10HZ

    I found that i need to divide by 5,000,000 to obtain this value

    but how exaclty is the clock converter set up???


    and how would i write it in VHDL??

    if someone does know, could you comment on the side to explain what each part does?


    Thanks!

    Zack
     
  2. shteii01

    AAC Fanatic!

    Feb 19, 2010
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  3. thatoneguy

    AAC Fanatic!

    Feb 19, 2009
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    Using hardware, use the input signal to a Flip-Flop, which divides by 2 each time.

    Or a few Counter IC's, using the signal as a clock, and the MSB of the first for the clock of the 2nd.
     
  4. imzack

    Thread Starter Active Member

    Nov 3, 2010
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    Ok that post of the VHDL code seemed pretty helpful, but i was confused on parts of it, is there somewhere that breaks down the code and comments on each line?

    im still kinda lost...
     
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