I need to make a clock divider in VHDL.
I am given a clock of 50MHZ
and i need to convert it to 10HZ

I found that i need to divide by 5,000,000 to obtain this value

but how exaclty is the clock converter set up???


and how would i write it in VHDL??

if someone does know, could you comment on the side to explain what each part does?


Thanks!

Zack

 

http://www.vlsibank.com/sessionspage.asp?titl_id=14763

You Google-Fu is weak!

 

Using hardware, use the input signal to a Flip-Flop, which divides by 2 each time.

Or a few Counter IC's, using the signal as a clock, and the MSB of the first for the clock of the 2nd.

 

Ok that post of the VHDL code seemed pretty helpful, but i was confused on parts of it, is there somewhere that breaks down the code and comments on each line?

im still kinda lost...